Interconnectable nanoscale computational stages

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C977S938000

Reexamination Certificate

active

11136935

ABSTRACT:
Embodiments of the present invention implement computing circuits comprising a number of interconnectable nanoscale computational stages. Each nanoscale computational stage includes: (1) a nanoscale logic array; and (2) a number of nanoscale latch arrays interconnected with the configurable logic array. Each nanoscale computational stage receives signals and passes the signals through the nanoscale logic array and to a nanoscale latch array. Signals output from the nanoscale latch array can be routed to another nanoscale computational stage or out of the computing circuit.

REFERENCES:
patent: 6417711 (2002-07-01), Fulkerson
patent: 6586965 (2003-07-01), Kuekes
patent: 6777982 (2004-08-01), Goldstein et al.
patent: 7073157 (2006-07-01), DeHon et al.
Leiserson, Charles E., et al., “Retiming Synchronous Circuitry,” digital; Systems Research Center, Aug. 20, 1986.
Touati, H.J., et al., “Computing the initial states of retimed circuits,” computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Jan. 1993.
Eckl, Klaus, et al., “A Practical Approach to Multiple-Class Retiming,” 1999, no month.
Singhal, Vigyan, et al., “The Case for Retiming with Explicit Reset Circuitry,” ICCAD 1996, no month.
Papaefthymiou, Marios C., “Understanding retiming through maximum average-weight cycles,” ACM Symposiusm, 1991, no month.
Kundu, Sandip, et al., “A Small Test Generator for Large Designs,” IEEE, 1992.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Interconnectable nanoscale computational stages does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interconnectable nanoscale computational stages, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnectable nanoscale computational stages will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3849787

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.