Interconnect with pressure sensing mechanism for testing semicon

Details Interconnect with pressure sensing mechanism for testing semicon Interconnect with pressure sensing mechanism for testing semicon

1997-02-24

1999-04-13

Dutton, Brian

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

257417, H01L 2358, H01L 2982

Patent

active

058941614

ABSTRACT:
An interconnect for testing semiconductor wafers, and a method and system for testing wafers using the interconnect are provided. The interconnect includes a substrate with contact members configured to establish temporary electrical communication with contact locations (e.g., bond pads, test pads) on the wafer. For flat contact locations (e.g., thin film bond pads), the contact members comprise raised members with penetrating projections. For bumped contact locations (e.g., solder bumps), the contact members comprise indentations with a conductive layer. The interconnect also includes a pressure sensing mechanism for monitoring and controlling contact forces between the interconnect and wafer. In an illustrative embodiment the pressure sensing mechanism comprises a piezoresistive or piezoelectric layer and resistance measuring device.

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