Interconnect with high aspect ratio plugged vias

Details Interconnect with high aspect ratio plugged vias Interconnect with high aspect ratio plugged vias

2006-12-01

2008-12-30

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S631000, C438S652000, C438S674000, C438S678000, C257SE23141, C257SE21175, C257SE21586

Reexamination Certificate

active

07470619

ABSTRACT:
Described is a method for forming a stackable interconnect. The interconnect is formed by depositing a first contact on a substrate; depositing a seed layer (SL) on the substrate; depositing a metal mask layer (MML) on the SL; depositing a bottom anti-reflection coating (BARC) on the MML; forming a photoresist layer (PR) on the BARC; removing a portion of the PR; etching the BARC and the MML to expose the SL; plating the exposed SL to form a first plated plug; removing the layers to expose the SL; removing an unplated portion of the SL; depositing an inter layer dielectric (ILD) on the interconnect; etching back the ILD to expose the first plated plug; and depositing a second contact on the first plated plug. Using the procedures described above, a second plated plug is then formed on the first plated plug to form the stackable plugged via interconnect.

REFERENCES:
patent: 6448171 (2002-09-01), Wang et al.
patent: 2003/0178666 (2003-09-01), Lee et al.
patent: 2007/0052101 (2007-03-01), Usami
patent: 2008/0075836 (2008-03-01), Chen et al.
Shigeki Wada, et al., “0.2um Fully-Aligned Y-shaped gate HJFET's with reduced gate-fringing capacitance fabricated using collimated sputtering and electroless Au-plating,” IEEE Transactions on Electron Devices, vol. 45, No. 8, Aug. 1998, pp. 1656-1662.
M.Y. Chan and T.C. Lo. “Electrochemical planarization by selective electroplating for embedded gold wiring in the sub-micron range,” 1995 IEEE Region 10 International Conference on Microelectronics and VLSI, pp. 287-290.
M. Hirano, et al., “Submicrometer Gold Interconnect wiring by sidewall electroplating technology,” Jpn J. Apply. Phys. 33, 1994, L553-L555.

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