Interconnect structure with gas dielectric compatible with...

Details Interconnect structure with gas dielectric compatible with... Interconnect structure with gas dielectric compatible with...

1997-10-09

2002-02-26

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S623000, C438S787000, C438S637000

Reexamination Certificate

active

06350672

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the formation of integrated circuit devices of the type that include multilevel interconnect structures.
2. Description of the Related Art
Modem integrated circuits include devices such as field effect transistors (FETs) or bipolar devices formed in and on a semiconductor substrate in combination with a multilevel interconnect structure formed above and in contact with the devices. The multilevel interconnect structure provides connections to and between different ones of the devices formed in the substrate and so is an increasingly important aspect of aggressive designs for integrated circuits. In many integrated circuits, the multilevel interconnect structure includes one or more arrays of wiring lines extending in parallel to provide connections to and between the devices in closely packed arrays of devices. Such arrays of devices are typical of integrated circuit memories and other aggressive circuit designs. Closely spaced, parallel wiring lines can provide undesirable levels of capacitive and inductive coupling between adjacent wiring lines, particularly for higher data transmission rates through the arrays of parallel wiring lines. Such capacitive and inductive coupling slow data transmission rates and increase energy consumption in a manner that can limit the performance of the integrated circuits. For some aggressive circuit designs, the delays and energy consumption associated with the circuit's interconnect structure are a significant limitation on the circuit's performance.
The complexity of modem interconnect structures has become a major cost component for integrated circuit designs. Various factors threaten to further increase the proportional expense of the interconnect structure within integrated circuits. For example, proposals have been advanced for substituting different interlayer and intermetal dielectric materials into multilevel interconnect structures to improve the coupling problem. The capacitive and inductive coupling between adjacent wiring lines is mediated by the dielectric material that separates the wiring lines. Present dielectric materials, such as silicon oxides deposited by chemical vapor deposition (CVD) from TEOS source gases, have comparatively high dielectric constants, and proposals have been made to replace these dielectric materials with dielectric materials having lower dielectric constants. Performance could be improved by replacing the higher dielectric constant materials with lower dielectric constant materials, with the theoretical minimum dielectric constant being provided by a gas or vacuum dielectric. Adoption of these alternate dielectric materials has not been completely satisfactory to this point in time, due to the increased cost and processing difficulty associated with these alternative materials.
One promising implementation of a multilevel interconnect structure using an air dielectric is described in the article by Anand, et al., NURA: A Feasible, Gas-Dielectric Interconnect Process, 1996
Symposium on VLSI Technology, Digest of Technical Papers
, 82-83 (1996). The interconnect structure and a method for making that structure are illustrated in
FIGS. 1-5
. The completed wiring structure is schematically illustrated in
FIG. 1
, which shows a substrate
10
having various devices (not shown) formed on its surface and covered by an interlayer dielectric
12
. First level wiring lines
20
,
22
extend along the surface of the interlayer dielectric
12
and are separated by air gaps
32
. The use of air gaps, as compared to more conventional dielectric materials, ensures that there is a minimal level of coupling between the adjacent first level wiring lines
20
,
22
. The first level air gaps are bounded on the bottom by the interlayer dielectric
12
and on the top by a thin layer of silicon oxide
30
. Contacts to the first level wiring lines
20
include vertical interconnects
36
that extend from the first level wiring lines
22
to the second level wiring lines
46
. The first level wiring lines
22
and the second level wiring lines
46
are separated vertically by via level air gaps
42
that surround the vertical interconnects
36
and which are bounded on the bottom and top by thin layers of silicon oxide
30
and
40
, respectively. These via level air gaps reduce the extent of capacitive and inductive coupling between the first level wiring lines
20
,
22
and the second level wiring lines
46
, as compared to more conventional solid dielectric materials. In a similar fashion, second level air gaps
52
, bounded on top and bottom by thin layers of silicon oxide
50
,
40
, are provided between the second level wiring lines
46
to reduce the level of capacitive and inductive coupling between the second wiring lines.
The device illustrated in
FIG. 1
is significant in that it reduces some of the problems with signal delays and energy dissipation associated with the multilevel interconnect structures used in high density integrated circuit designs. The methods used to manufacture the device shown in
FIG. 1
are also significant and are now described with reference to
FIGS. 2-5
. Referring first to
FIG. 2
, devices are formed in the desired configuration in and on the substrate
10
and then the substrate is covered with an interlayer dielectric
12
. Vias may be formed through the interlayer dielectric
12
to provide connections to the device formed in the substrate (not shown) and the first level wiring lines may be formed in a manner that fills those vias or so that the first level wiring lines will make contact with the interconnects that fill those vias. First level wiring lines are formed in a modified damascene process. First, a layer of carbon is deposited over the surface of the interlayer dielectric and then a mask (not shown) is provided on the surface of the carbon layer
14
, typically using photolithography to form a photoresist mask. The photoresist mask exposes the surface of the carbon layer
14
in a pattern corresponding to the arrangement desired for the first level wiring lines. Anisotropic etching is performed to provide trenches
16
in the carbon layer
14
and the mask is removed to provide the structure shown in FIG.
2
.
Metal is then deposited over the
FIG. 2
structure and then the excess metal is removed to define first level wiring lines
20
,
22
, as shown in FIG.
3
. Next, a thin layer of silicon oxide
30
is provided over the first level wiring lines
20
,
22
and the remaining portions of the carbon layer
14
. Preferably, the thin silicon oxide layer
30
is deposited by sputtering to a thickness of approximately 500 Å. Next, the device is placed in a furnace holding an oxygen ambient and heated to a temperature of 400-450° C. for approximately two hours. In this environment, oxygen readily diffuses through the thin oxide layer
30
to react with the carbon layer
14
, forming CO
2
which diffuses back through the thin oxide layer and escapes. After the two hour ashing period, the entire carbon layer
14
is consumed, leaving behind air gaps
32
between the oxide layer
30
and the interlayer dielectric
12
and separating the first level wiring lines
20
,
22
, as shown in FIG.
4
. This process can then be repeated to produce the multilevel interconnect structure shown in FIG.
5
. Thus, a via level of carbon is deposited and patterned to define the vias through which vertical interconnects are to be formed. The oxide within the vias is removed, metal is deposited and etched back to provide the vertical interconnects within the via level carbon layer, and then a thin layer of oxide
40
is deposited over the carbon layer. Ashing is performed to remove the oxide layer, leaving via level air gaps
42
between the vertical interconnects
36
and between the oxide layers
30
,
40
. A second level of carbon
44
is deposited and patterned to define second level wiring line trenches, the oxide layer
40
is removed as appropriate over the vertical interconnects

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