Interconnect structure using a combination of hard...

Details Interconnect structure using a combination of hard... Interconnect structure using a combination of hard...

1999-04-13

2001-05-29

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S760000, C438S701000

Reexamination Certificate

active

06239019

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of semiconductor processing. More specifically, this invention relates to a structure and method for forming an integrated circuit device having a multilayer interlayer dielectric structure.
BACKGROUND OF THE INVENTION
A semiconductor integrated circuit is built by layering electrically conductive materials patterned in electrical circuitry over a base transistor structure on a semiconductor substrate. The electrically conductive materials are in separate planes, with electrical pathways, or vias, electrically connecting the various layers of electrically conductive materials. Insulating material is held between the planes of electrically conductive material around the vias as well as within the trenches in the circuit pattern of a layer of electrically conductive material. The traditionally used insulating material is silicon dioxide, having a dielectric constant of approximately 4. Silicon dioxide is useful because, among other reasons, it is thermally stable and mechanically strong. However, it has been known that better device performance is achieved with lower capacitance between conductive lines within a layer of conductive material. Lower capacitance is achieved using a material having a lower dielectric constant. One such material for potential replacement of silicon dioxide because of its lower dielectric constant property is organic polymer.
In a typical process using organic polymer as the interlayer dielectric, the sequence begins with a partially fabricated integrated circuit substrate containing a patterned electrically conductive layer. An organic polymer is deposited within the trenches or spacings within the patterned electrically conductive layer as well as to a predetermined thickness above the top surface of the electrically conductive layer. The organic polymer is planarized to flatten the top surface a distance above the surface of the electrically conductive layer. Vias are formed into the organic polymer and electrically conductive plugs are formed within the vias. A second electrically conductive layer is formed on the surface of the organic polymer including the electrically conductive plugs. The process is repeated by patterning the second electrically conductive layer, depositing organic polymer, planarizing the organic polymer, opening vias in the organic polymer, forming plugs in the vias, and so on. Further details on the just-described process flow can be found in Chiang et al, “A Novel Interconnect Structure Using a Hard Mask for Low Dielectric Constant Materials”, U.S. Ser. No. 670,624.
To make practical use of organic polymer as the insulating material in a semiconductor device is problematic. Silicon dioxide, the traditionally used material, is about 50 times harder than organic polymer. The elastic modulus of silicon dioxide is about 20 times greater than organic polymer. Organic polymer is mechanically weak. compared with silicon dioxide. It is prone to bending and twisting under stress, causing shifting and cracking of adjacent electrically conductive materials. Organic polymer also has significantly lower thermal conductivity than silicon dioxide (3-30 times lower), thus making organic polymer worse for heat dissipation. Poor heat dissipation leads to poor transistor performance in semiconductor integrated circuits. Moreover, organic polymer tends to be chemically reactive to solvents and gas plasma compared with silicon dioxide. This can cause difficulties during the preparation of the vias for accepting electrically conductive plugs because the preparation step includes plasma etching.
It would be advantageous to enable the use of organic polymer for insulating material in semiconductor devices to receive the benefits of its low dielectric constant property, while not otherwise harming structural and thermal integrity of the device.
SUMMARY OF THE INVENTION
This invention is a novel structure for an integrated circuit device utilizing two different insulating materials to form the insulation above and within electrically conductive features. There is a layer of electrically conductive material containing a pattern. A first insulating material substantially fills the trenches in the pattern of the electrically conductive layer. A second insulating material is over the patterned electrically conductive layer. A method of fabricating such a structure is also disclosed. There is provided a patterned electrical conductive material and the trenches of the pattern are filled with a first insulating material. The first insulating material is planarized, and a second insulating material is deposited over the electrically conductive layer.


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patent: 5155576 (1992-10-01), Mizushima
patent: 5389814 (1995-02-01), Srikrishnan et al .
patent: 5488015 (1996-01-01), Havemann et al.
patent: 5500558 (1996-03-01), Hayashide
patent: 5616959 (1997-04-01), Jeng
patent: 5886410 (1999-03-01), Chiang et al.

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