Interconnect structure to reduce stress induced voiding effect

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

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C257S758000, C257S773000, C438S619000

Reexamination Certificate

active

10984050

ABSTRACT:
An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.

REFERENCES:
patent: 6054770 (2000-04-01), Toyoda et al.
patent: 6307268 (2001-10-01), Lin
patent: 6342733 (2002-01-01), Hu et al.
patent: 6368967 (2002-04-01), Besser
patent: 2002/0076903 (2002-06-01), Kondo et al.
Ogawa, et al., “Stress-Induced Voiding Under Vias Connected to Wide Cu Metal Leads,” 40th Annual International Reliability Physics Symposium (2002) pp. 312-321.

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