Interconnect structure for semiconductor devices

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S774000, C257SE23011, C257SE23142, C257SE23145, C257SE23169, C257SE23175, C438S584000, C438S585000, C438S623000, C438S634000, C438S637000, C438S641000, C438S653000

Reexamination Certificate

active

07834458

ABSTRACT:
A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.

REFERENCES:
patent: 5126574 (1992-06-01), Gallagher
patent: 5238874 (1993-08-01), Yamada
patent: 5403779 (1995-04-01), Joshi et al.
patent: 6046108 (2000-04-01), Liu et al.
patent: 6071808 (2000-06-01), Merchant et al.
patent: 6136682 (2000-10-01), Hedge et al.
patent: 6287970 (2001-09-01), Merchant et al.
patent: 6368961 (2002-04-01), Lopatin et al.
patent: 6521523 (2003-02-01), Lee et al.
patent: 6607976 (2003-08-01), Chen et al.
patent: 6660634 (2003-12-01), Ngo et al.
patent: 6740916 (2004-05-01), Ireland et al.
patent: 2002/0055223 (2002-05-01), Kutsunai et al.
patent: 2003/0173671 (2003-09-01), Hironaga et al.
patent: 2005/0014360 (2005-01-01), Yu et al.
patent: 2006/0118962 (2006-06-01), Huang et al.
patent: 2007/0075428 (2007-04-01), Wang et al.
Martin et al. “Integration of SiCN as a Low k Etch Stop and Cu Passivation in a High Performance Cu/Low k Interconnect” , International Interconnect Technology Conference (IITC) Jun. 2002.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Interconnect structure for semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interconnect structure for semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnect structure for semiconductor devices will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4186069

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.