Interconnect structure for FPGA with configurable delay locked l

Details Interconnect structure for FPGA with configurable delay locked l Interconnect structure for FPGA with configurable delay locked l

1998-08-19

2000-08-22

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, 326 40, 326 39, 326 38, 326 37, 326 47, 326101, H03K 19177

Patent

active

061078263

ABSTRACT:
A field programmable gate array (FPGA) is provided that includes a plurality of pads and a plurality of delay locked loops (DLLs). Programmable connections enable any one of the DLLs to have multiple pads as inputs. Programmable connections also enable the DLLs to be selectively connected to one another. Programmable connections further enable the pads to be selectively connected to general interconnect circuitry or global clock drivers of the FPGA. Programmable connections are also provided for selectively connecting the DLLs to the global clock drivers. This FPGA structure enables the pads to be configured to receive either clock or non-clock signals. This structure also enables the FPGA to operate as a clock mirror, and to generate one clock signal from another clock signal on the FPGA.

REFERENCES:
patent: 5646564 (1997-07-01), Erickson et al.
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patent: 5771264 (1998-06-01), Lane
patent: 5825197 (1998-10-01), Lane et al.
Microelectronics Group, Lucent Techologies, Inc., Preliminary Data Sheet, May 1998, pp. 69-80, ORCA OR3Cxx (5 V), and OR3Txxx (3.3 V) Series Field-Programmable Gate Arrays, available from Microelectronics Group, Lucent Technologies, Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103.
"Actel ES Family Digital Phase Lock Loop Usage", by Joe Landry, Sep. 17, 1996, pp. 1-5, available from Actel Corporation, 955 East Arques Avenue, Sunnyvale, CA 94086-4533.
"Actel's Reprogrammable SPGAs", Oct. 10, 1996, pp. 1-8, available from Actel Corporation, 955 East Arques Avenue, Sunnyvale, CA 94086-4533.

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