Interconnect structure for an integrated circuit and method...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S625000, C438S637000

Reexamination Certificate

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07151051

ABSTRACT:
An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.

REFERENCES:
patent: 5737259 (1998-04-01), Chang
patent: 5783864 (1998-07-01), Dawson et al.
patent: 5835396 (1998-11-01), Zhang
patent: 6653704 (2003-11-01), Gurney et al.
patent: 6713835 (2004-03-01), Horak et al.
patent: 7071545 (2006-07-01), Patel et al.
patent: 2002/0145201 (2002-10-01), Armbrust et al.

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