Interconnect model-order reduction method

Details Interconnect model-order reduction method Interconnect model-order reduction method

2005-08-08

2008-10-14

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07437689

ABSTRACT:
An interconnect model-order reduction method reduces a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select an order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, with analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm. Therefore, the residual error information may be taken as a reference for the order selection scheme used in Krylov subspace model-order algorithm.

REFERENCES:
patent: 6023573 (2000-02-01), Bai et al.
patent: 6041170 (2000-03-01), Feldmann et al.
patent: 6687658 (2004-02-01), Roychowdhury
patent: 6810506 (2004-10-01), Levy
patent: 2005/0235023 (2005-10-01), Lee et al.
patent: 2006/0100831 (2006-05-01), Lee et al.
patent: 2006/0282799 (2006-12-01), Chu et al.
Pillage, L. T. and Rohrer, R. A., “Asymptotic Waveform Evaluation for Timing Analysis”, IEEE Transactions on Computer-Aided Design, vol. 9, No. 4, Apr. 1990, pp. 352-366.
Grimme, E. J., “Krylov Projection Methods for Model Reduction”, University of Illinois Urbana-Champaign, 1997, pages cover p. 213.
Feldmann, P. and Freund, R. W., “Efficient Linear Circuit Analysis by Padé Approximation via the Lanczos Process”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, No. 5, May 1995, pp. 639-649.
Freund, R. W. and Feldmann, P., “The SyMPVL Algorithm and Its Applications to Interconnect Simulation”, IEEE 1997, pp. 113-116.
Odabasioglu, A., Celik, M. and Pileggi, L. T., “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, No. 8, Aug. 1998, pp. 645-654.
Odabasioglu, A., Celik, M. and Pileggi, L. T., “Practical Considerations for Passive Reduction of RLC Circuits”, IEEE 1999, pp. 214-219.
Bai, Z., Slone, R. D., Smith, W. T. and Ye, Q., “Error Bound for Reduced System Model by Padé Approximation via the Lanczos Process”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, No. 2, Feb. 1999, pp. 133-141.
Freund, R. W., “Krylov-subspace methods for reduced-order modeling in circuit simulation”, Bell Laboratories, Numerical Analysis Manuscript No. 99-3-17, Nov. 1999, pp. 1-36.
Wang, J. M., Chu, C.C., Yu, Q. and Kuh, E. S., “On Projection-Based Algorithms for Model-Order Reduction of Interconnects”, IEEE Transactions on Circuits and Systems—I: Fundamental Theory and Applications, vol. 49, No. 11, Nov. 2002, pp. 1563-1585.

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