Interconnect integrity verification

Details Interconnect integrity verification Interconnect integrity verification

2004-12-07

2008-09-09

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07424690

ABSTRACT:
A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using a layout tool that produces a layout verses schematic reference file, mapping the reference file to the net list to create a mapping file, and analyzing the mapping file to verify that the layout meets various criteria. Each block may be verified using simulation tools that are appropriate for that piece of the overall circuit, and using conditions that may maximize the strain on the circuit. The results from the simulations are compared to the physical layout to determine if the physical layout is able to properly conduct the electrical signals.

REFERENCES:
patent: 5901066 (1999-05-01), Hong
patent: 5943487 (1999-08-01), Messerman et al.
patent: 6298469 (2001-10-01), Yin
patent: 2003/0069722 (2003-04-01), Beattie et al.

Affiliated with

Also associated with

Rating

Interconnect integrity verification does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interconnect integrity verification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnect integrity verification will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3982083