Interconnect for a GMR memory cells and an underlying...

Details Interconnect for a GMR memory cells and an underlying... Interconnect for a GMR memory cells and an underlying...

2009-04-03

2010-10-19

Monbleau, Davienne (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S427000, C257SE21665, C438S689000, C438S003000, C365S158000

Reexamination Certificate

active

07816718

ABSTRACT:
A conductive plug located in a planar dielectric layer, under GMR memory cells, are used to directly connect the lower ferromagnetic layer of one of the GMR memory cell and a conductive layer under the planar dielectric layer.

REFERENCES:
patent: 6783995 (2004-08-01), Hineman et al.
patent: 6911156 (2005-06-01), Grynkewich et al.
patent: 2002/0146849 (2002-10-01), Durcan et al.
patent: 2003/0042562 (2003-03-01), Giebeler et al.
patent: 2004/0188731 (2004-09-01), Boeve
patent: 2005/0161715 (2005-07-01), Perner et al.
patent: 2007/0242394 (2007-10-01), Gill

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