Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1998-03-20
1999-11-16
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
G06F 1100
Patent
active
059876298
ABSTRACT:
A method and apparatus for detecting and isolating an interconnect fault in a packet switched network generates a parity check error code for status messages which are used for flow control in a packet switched network. The packet switched network uses a reverse flow control method wherein status messages are sent locally between adjacent nodes. A receiving node uses status messages to inform an adjacent node of the availability of the input buffers located in the receiving node. Included in the status message is a parity check code that is sent sequentially with the status message using two phases of a clock. The parity check code is a one bit parity check for each bit of the status message. Faults on the local interconnect are detected at the receiving node by performing a one bit parity check on the received status message using the accompanying parity code. Because the status message and the parity check code are transmitted over the same physical bit connections, the one bit parity checks detects any "stuck at" or "open" faults in the link.
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Larson Jeffrey D.
Mu Albert
Sastry Raghu
Schober, Jr. Richard L.
Slice John R.
Beausoliel, Jr. Robert W.
Elisca Pierre E.
Fujitsu Limited
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