Interconnect-driven physical synthesis using persistent...

Details Interconnect-driven physical synthesis using persistent... Interconnect-driven physical synthesis using persistent...

2008-06-24

2010-12-14

Doan, Nghia M (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S013000, C703S014000

Reexamination Certificate

active

07853915

ABSTRACT:
A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.

REFERENCES:
patent: 5856927 (1999-01-01), Greidinger et al.
patent: 6353918 (2002-03-01), Carothers et al.
patent: 6622291 (2003-09-01), Ginetti
patent: 7222311 (2007-05-01), Kaufman et al.
patent: 7337100 (2008-02-01), Hutton et al.
patent: 2003/0177455 (2003-09-01), Kaufman et al.
patent: 2004/0243964 (2004-12-01), McElvain et al.
patent: 2007/0016881 (2007-01-01), Gregory et al.
Pan et al.: “FastRoute: A Step to Integrate Global Routing Into Placement”, ICCAD '06, Nov. 5-9, 2006, San Jose, CA, Copyright 2006, 8 pgs.
Pedram et al.: “Layout Driven Technology Mapping”, 28thACM/IEEE Design Automation Conference, 1991 ACM, pp. 99-105.
Alpert et al.: “Prim-Dijkstra Tradeoffs for Improved Performance-Driven Routing Tree Design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, No. 7, Jul. 1995, pp. 890-896.
Pan et al.: “IPR: An Integrated Placement and Routing Algorithm”, DAC 2007, Jun. 4-8, 2007, San Diego, CA, Copyright 2007, pp. 59-62.
Stenz et al.: “Performance Optimization by Interacting Netlist Transformations and Placement”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, No. 3, Mar. 2000, pp. 350-358.
Cheng: “RISA: Accurate and Efficient Placement Routability Modeling”, 1994 ACM, pp. 690-695.
Alpert et al.: “Fast and Flexible Buffer Trees That Navigate the Physical Layout Environment”, DAC 2004, Jun. 7-11, 2004, San Diego, CA, Copyright 2004, pp. 24-29.
Chu et al.: “FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, No. 1, Jan. 2008, pp. 70-83.
Ren et al.: “Sensitivity Guided Net Weighting for Placement-Driven Syntheses”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, No. 5, May 2005; pp. 711-721.
Chen et al.: “Refined Single Trunk Tree: A Rectilinear Steiner Tree Generator for Interconnect Prediction”, SLIP'02, Apr. 6-7, 2002, San Diego, CA Copyright 2002, pp. 85-89.
Chowdhary et al.: “How Accurately Can We Model Timing in a Placement Engine?”, DAC 2005, Jun. 13-17, 2005, Anaheim, CA, Copyright 2005, pp. 801-806.

Affiliated with

Also associated with

Rating

Interconnect-driven physical synthesis using persistent... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interconnect-driven physical synthesis using persistent..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnect-driven physical synthesis using persistent... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4202085