Interconnect dielectric tuning

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S614000, C438S669000

Reexamination Certificate

active

07081406

ABSTRACT:
An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

REFERENCES:
patent: 5559055 (1996-09-01), Chang et al.
patent: 6198170 (2001-03-01), Zhao

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