Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-07-25
2006-07-25
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S614000, C438S669000
Reexamination Certificate
active
07081406
ABSTRACT:
An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.
REFERENCES:
patent: 5559055 (1996-09-01), Chang et al.
patent: 6198170 (2001-03-01), Zhao
Catabay Wilbur G.
Gu Shiqun
Hsia Wei-Jen
Lin Hong
Lo Wai
Dang Phuc T.
LSI Logic Corporation
Luedeka Neely & Graham PC
LandOfFree
Interconnect dielectric tuning does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interconnect dielectric tuning, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnect dielectric tuning will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3608354