Interconnect capacitive effects estimation

Details Interconnect capacitive effects estimation Interconnect capacitive effects estimation

1999-03-26

2001-11-06

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06314546

ABSTRACT:

FIELD OF THE INVENTION
This application relates to integrated circuit design automation and, specifically, to gate interconnect load estimation.
BACKGROUND OF THE INVENTION
Integrated circuit design includes selection and layout of gates also known as cells. The interconnections between the multiplicity of gates in an integrated circuit form signal paths. In most cases, the interconnections between gates form an interconnect tree (as shown in FIG.
1
). The resistive, capacitive and inductive attributes of interconnect lines form gate loads at the respective gate outputs and contribute to signal time delays.
With interconnect delays dominating overall path delays for deep-submicron integrated circuits, heuristics for logic synthesis and layout optimization need to accurately model interconnect effects. Accurate estimations of gate delay and slew time are required for a number of signal integrity and reliability checks. In synthesis and floorplanning, pre-layout gate delay estimation capability is needed. In post-layout timing analysis, existing accurate gate delay estimates are not efficient enough to be used in the typical incremental synthesis, layout or in-place optimization loop or during performance-driven area routing. In either context, accurate estimations of gate delay and slew time at the gate output, depend closely on an accurate model for the admittance of an interconnect tree load at the gate output. The present invention addresses these and related issues.
SUMMARY OF THE INVENTION
The present invention provides a new non-iterative approach for estimating interconnect capacitive effects. This approach includes determining an effective capacitance that represents the interconnect capacitive effects at an output of a driving gate (hereafter “gate”). The effective capacitance estimation is preceded by a gate modeling.
The gate is modeled using, for example, a Thévenin equivalent circuit to solve a closed-form equation for the voltage response at the gate output. A closed-form equation is a single equation requiring only one iteration for deriving a solution.
Effective capacitance determination in accordance with this non-iterative approach involves modeling of an interconnect tree load at the gate output (i.e., the gate load). The gate load modeling uses an accurate RC Π model or open-ended (heuristic) RC Π model (hereafter collectively referred to as the “RC Π model”). The use of an open-ended RC Π model eliminates the need for moment computations at the gate output. The use of an accurate RC Π model requires a determination of the first three moments of the gate load admittance. The gate load modeling uses, in addition, a single capacitance model. Then the effective capacitance value is closely estimated by matching the RC Π model response with that of the single capacitance model.
The non-iterative approach includes a method for estimating the interconnect capacitive effects. The method includes modeling the gate and estimating an effective capacitance for the interconnect capacitive effects. The effective capacitance estimation includes modeling the gate load at an output of the gate. The gate load modeling includes approximating an admittance of the gate load to a single capacitance model in addition to approximating the admittance of the gate load to a Π model. The gate load modeling also includes matching a gate response for the Π model with the gate response for the single capacitance model to determine the effective capacitance.
Another aspect of the method for estimating the interconnect capacitive effects includes modeling the gate using an equivalent circuit, and modeling the load at an output of the gate. The gate load modeling includes determining Π model parameters that represent the load at the output of the gate. The parameters are associated with a response at the gate output. The effective capacitance estimation method further includes modeling a single capacitive load at the output of the gate. The single capacitive load modeling includes determining a gate delay for a threshold time at a threshold voltage. This delay determination accounts for the input voltage waveform, the voltage response at the gate output and the Π model parameters. The single capacitance modeling the capacitive load is determined using the threshold time. The effective capacitance is then derived taking into account the single capacitance, a total capacitance of the gate load, an intrinsic gate delay and a gate load delay for the total capacitance as a load.
For logic synthesis and layout optimization, this non-iterative approach models interconnect capacitive effects faster and with little or no loss of accuracy. Hence, this non-iterative approach is suitable as a step within the analysis loop for performance driven iterative layout optimization.
The non-iterative approach can, for example, be suitably implemented in timing analysis tools. Such tools are used for analysis and optimization of critical paths in integrated circuits design, including microprocessors design. Moreover, a computer system can be used in which an embodiment of the present invention is implemented
Advantages of the invention will be set forth, in part, in the description that follows and, in part, will be understood by those skilled in the art from the description herein. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims and equivalents.


REFERENCES:
patent: 5285165 (1994-02-01), Renfors et al.
patent: 5544068 (1996-08-01), Takimoto et al.
patent: 5790415 (1998-08-01), Pullela et al.
patent: 5841672 (1998-11-01), Spyrou et al.
Arunachalam et al., “CMOS Gate Delay Models for General RLC Loading,” 1997 IEEE, pp. 224-229.*
Hafed et al., “CMOS Inverter Current and Delay Model Incorporating Interconnect Effects,” 1998 IEEE, pp. 86-89.*
Kahng et al., “Improved Effective Capacitance Computations for Use in Logic and Layout Optimization,” Proc. 12th Int'l Conference on VLSI Design, Jan. 1999 [no page numbers].*
Krauter et al., “Including Inductive Effects in Interconnect Timing Analysis,” IEEE 1999 Custom ICs Conference, pp. 445-452.*
Semiconductor Industry Association, National Technology Roadmap for Semiconductors, pages Table of Contents, pp. 1-3, 7-19, 23-113, 163-178, Appendix B1-C8, 1994.
Personal communication, SIA NTRS 1997 Revision, Design and Test Technology Working Group (chairs: R. Howard, P. Verhofstadt), 1997, Table of Contents, pp. 1-3, 8, 10-17, 25-38, 94-109, Appendix B, C and D, 1997.
C. J. Alpert and A. Devgan, “Wire Segmenting for Improved Buffer Insertion”, Proc. Design Automation Conf., pp. 558-593, Jun. 1997.
D. P. LaPotin, U. Ghoshal, E. Chiprout, S. R. Nassif, “Physical Design Challenges For Performance”, International Symposium on Physical Design, pp. 225-226, Apr. 1997.
L. Scheffer, “A Roadmap Of CAD Tool Changes For Sub-Micron Interconnect Problems”, International Symposium on Physical Design, pp. 104-109, Apr. 1997.
R. F. Sechler, “Interconnect design with VLSI CMOS”, IBM Journal of Research and Development, pp. 23-31, Jan.-Mar. 1995.
J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen, Analysis And Justification Of A Simple, Practical 2½-D Capacitance Extraction Methodology, Proc. Design Automation Conference, pp. 627-632, Jun. 1997.
L. Gwennap, “IC Vendors Prepare for 0.25-Micron Leap”, Microprocessor Report, pp. 11-15, Sep. 16, 1996.
S.Y. Oh, K.-J. Chang, N. Chang and K. Lee, “Interconnect Modeling And Design In High-Speed VLSI/ULSI Systems”, Proc. International Conference on Computer Design: VLSI in Computers and Processors, pp. 184-189, Oct. 1992.
H.B. Bakoglu, “Circuits, Interconnections, and Packaging for VLSI,” Addison-Wesley Publishing Company, 1990, pp. 202-207, 212-215, 282-285.
A. Devgan, “Efficient Coupled Noise Estimation for On-Chip Interconnects,” IEEE International Conference on Computer-Aided Design, Nov. 1997, pp. 147-151
G.A. Katopis and H.H. Smith, “Coupled Noise Predictors for Lossy Interc

Affiliated with

Also associated with

Rating

Interconnect capacitive effects estimation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interconnect capacitive effects estimation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnect capacitive effects estimation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2599379