Interconnect bus

Details Interconnect bus Interconnect bus

2001-06-19

2004-04-06

Ray, Gopal C. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S300000, C709S251000, C370S258000

Reexamination Certificate

active

06718421

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to bus architectures. More specifically, the present invention relates to a communication method and bus design that interconnect a plurality of components in a ring configuration with segments of the bus chaining from one component to another so as to reduce the amount of global wiring between components.
2. Background and Related Art
Integrated circuits usually require one or more buses to interconnect each of the various functional components within the integrated circuit. In many circumstances, these types of buses are referred to as “global wire,” because generally they run between each and every functional component. For example, control bus
211
and memory bus
212
, both of
FIG. 2
, use global wire buses to interconnect the components of ASIC
210
. (Note that referring to control bus
211
and memory bus
212
as global wire is not an admission in any degree that
FIG. 2
constitutes prior art with respect to the present invention.)
Buses that use global wire generally provide favorable performance characteristics and are able to move large amounts of data over a relatively short period of time. A bus controller and a processor may be used to manage a global wire bus, with all transactions passing through the bus controller and processor. In other circumstances, a direct memory access controller may be used to provide components with direct access to each other, allowing the bus controller and processor to be bypassed. Some bus operations between components may be relatively insensitive to performance considerations while others are highly dependent on bus speed. For example, the speed with which a component's control register is read or written may impact overall system performance only minimally whereas the speed with which an image is transferred to a graphics component may determine overall system performance.
The amount of global wire is a significant design constraint due to routing and signal quality considerations. In at least some circumstances, global wire may complicate routing based simply on the large number of signals that are routed throughout an integrated circuit. As a result, even though other factors urge one component layout, routing global wire may be the determining factor in having to select an alternate component layout. For example, wire length is a significant factor in determining a maximum clock rate for an integrated circuit, with shorter wire lengths corresponding to faster clock rates. If routing problems caused by global wire dictate component layout, clock rates for the integrated circuit may need to be slowed so that longer wires do not introduce timing problems.
SUMMARY OF THE INVENTION
The present invention extends to a communication method and a bus design that interconnect a plurality of components in a ring configuration with segments of the bus chaining from one component to another so as to reduce the amount of global wiring between components. One of the components serves as a beginning point and an ending point for the ring. The bus includes unidirectional signal lines that carry data objects and tags in one direction, and carry flow control information in the opposite direction. Tags accompany each data object and determine how a component interprets the data object when received by a component.
Components may control the flow of data objects in upstream bus segments using flow control. Flow control may be used to provide a component with an opportunity to satisfy a read request, to process a write request, to control upstream bus segments in response to flow control received from a downstream component, etc. For example, a component may be unable to satisfy a read request or to process a write request at the time the request is received. As noted, flow control propagates upstream, whereas data objects propagate downstream.
A bus interface may be included with each component to interface with the signal lines and identify the component. The bus design and communication method simplify overall circuit design because they allow individual components to be developed in relative isolation and integrated at a later time. Chaining components in a ring configuration significantly reduces the need for global wire. Furthermore, final component placement is dictated less by global wire constraints and may consider and account for other design parameters.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The features and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.


REFERENCES:
patent: 4177510 (1979-12-01), Appell et al.
patent: 5659781 (1997-08-01), Larson
patent: 6349092 (2002-02-01), Bisson et al.
“Quantifying the benefit of configurability in circuit-switched WDM ring networks” by B. Schein and E. Modiano. (Abstract only).*
Guoping Lu n-Dimensional Processor Arrays with Optical dBuses The Journal of Supercomputing vol. 16, No. 3, Jul. 2000 pp. 149-162.
Jason Cong, Lei He, Cheng-Koh, and Zhigang Pan Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers Nov. 9-13, 1997 pp. 628-633.
Pasi Kolinummi, Timo Hamalainen, Jukka Saarinen Chained Backplane Communinication Architecture For Scalable Multiprocessor Sytems Journal of Systems Architecture vol. 46, No. 11, Sep. 2000 pp. 955-971.

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