Interconnect-aware integrated circuit design

Details Interconnect-aware integrated circuit design Interconnect-aware integrated circuit design

2006-07-18

2006-07-18

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07080340

ABSTRACT:
In a system10for designing an integrated circuit, a preliminary design of the integrated circuit is defined and critical interconnect lines in the preliminary design are identified. Further, any critical interconnect lines which are affected by crossing lines in the preliminary design are identified, and a transmission line model35is defined to represent each critical interconnect line. A layout design of the integrated circuit, comprising circuit components and parameters thereof, is then defined using the preliminary design and the transmission line model35for each critical interconnect line. Component parameters are then extracted from the layout design for simulation of the design using the extracted component parameters. During this design process, for each transmission line model35representing a critical interconnect line affected by a crossing line, an environment terminal36is provided. The environment terminal36comprises a connection to the model35via at least one circuit component representing the effect of the crossing line on the model. The environment terminal36is connected to the appropriate crossing line in the integrated circuit design, whereby crossing line effects are accommodated in the design process.

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Goren, D., et al., “On-chip Interconnect-Aware Design and Modeling Methodology, Based on High Bandwidth Transmission Line Devices”, DAC 2003, Jun. 2-6, 2003, Anaheim, CA, USA, Copyright 2003 ACM 1-58113-688-9/03/0006.

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