Intercommunicating apparatus for duplex system capable of...

Details Intercommunicating apparatus for duplex system capable of... Intercommunicating apparatus for duplex system capable of...

2006-01-24

2008-07-08

Torres, Joseph D. (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S799000

Reexamination Certificate

active

07398447

ABSTRACT:
A parity generating circuit in a 0 side receives input signals on respective signal lines and produces a parity bit based on the input signals. A parallel/serial converting circuit multiplexes parallel signals (or input signals) and the parity bit into a serial signal with reference to a timing signal. A serial/parallel converting circuit in a 1 side reproduces parallel signals and a parity signal and produces a parity check timing signal. A parity checking circuit checks a parity of the parallel signals by the use of the parity signal. If normal, a state holding circuit holds outputs of the parity checking circuit as a state signal. If abnormal, held content of the state holding circuit is cleared.

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