Boots – shoes – and leggings
Patent
1995-12-27
1997-09-09
Teska, Kevin J.
Boots, shoes, and leggings
364489, 364490, G06F 1750
Patent
active
056662904
ABSTRACT:
A method of optimizing the placement of components of an integrated circuit to ensure that all circuit paths will meet their timing criteria, as well as to minimize area and total wire length is disclosed. The method employs a non-constant net weighting distribution along critical paths to encourage a mincut algorithm to place components so that path lengths are minimized as well as the entire nets coupled to paths. The magnitude of weights assigned are commensurate with the slack the path has with respect to its maximum delay constraint, as well as the level of method iteration. Any nets not deemed critical are assigned a minimum capacitance constraint to prevent them from becoming critical as a function of actual placement. Weights assigned to capacitively constrained nets are inversely proportional to the difference between the maximum capacitance allowed and the estimated capacitance of the current placement. A novel manner of estimating the propagation delay along the interconnect of the critical path is implemented. A novel weighting of driver/buffer pairs ensure that the most sensitive nets of the pairs are kept short.
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Ashtaputre Sunil
Li Ying-Meng
Garbowski Leigh Marie
Teska Kevin J.
VLSI Technology Inc.
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