Interactive memory allocation in a behavioral synthesis tool

Details Interactive memory allocation in a behavioral synthesis tool Interactive memory allocation in a behavioral synthesis tool

2001-04-20

2003-08-26

Crane, Sara (Department: 2811)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06611952

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to behavioral synthesis tools for creating integrated circuits, and more particularly relates to behavioral synthesis tools that allow for interactive memory allocation during the design of integrated circuits.
BACKGROUND
The design of complex computer hardware no longer begins with a circuit diagram. Instead, it begins with a software program that describes the behavior or functionality of a circuit. This software program is written in a hardware description language (HDL) that defines an algorithm to be performed with limited implementation details. Designers direct behavioral synthesis tools to generate alternate architectures by modifying constraints (such as clock period, number and type of data path elements, and desired number of clock cycles). Behavioral synthesis tools convert the HDL program into a register transfer level (RTL) description. The RTL description is used to ultimately generate a netlist that includes a list of components in the circuit and the interconnections between the components. This netlist is used to create the physical integrated circuit.
In HDL source code, arrays provide a powerful and convenient method for modeling the behavior of memories. That is, behavioral descriptions are used to manipulate groups of data in an abstract manner using arrays. These arrays are, under the control of the designer, mapped to memory. Behavioral synthesis tools automatically construct the logic to control the memory, freeing the designer to explore architectures using different memories with different characteristics (e.g., synchronous versus asynchronous, single port versus dual port), and make intelligent decisions about an appropriate implementation for a design.
An example HDL source code is shown in Table 1 below that declares three variables, a, b, and c, that are arrays. Each array contains 1024, 8-bit words. The code first declares a “subtype” to define the type of each element in the array. The code then defines a “type” to represent the array itself. Finally, the variables are declared, each variable representing an array.
TABLE 1
SUBTYPE word IS unsigned (7 DOWNTO 0);
TYPE array_type IS ARRAY (integer RANGE <>) of word,
VARIABLE a, b, c: array_type (0 to 1023)
Generally, the variables are accessed using loops, such as the loop shown below in Table 2. For variables that are mapped to a memory, a read or write of a variable corresponds to a memory read or write that will be implemented in hardware. When an array is mapped to memory, each element in the array is mapped to a memory location. For example, a(0) maps to address 0, a(1) maps to address 1 and a(1023) maps to address 1023, etc.
TABLE 2
FOR i IN 0 TO 15 LOOP
 a(i) := b (i) * c(i) +4;
END LOOP;
To map variables to a memory, the designer must specifically assign the variables to a memory in source code and specify the type of memory and other memory parameters (e.g., packing mode). This is accomplished using a set of HDL attributes or directives. For example, Synopsis® (tools use a “pragma” statement.
There are essentially three types of packing modes: explicit (also called absolute), packed (also called compact), and base aligned. In the explicit packing mode, the array indices are taken as exclusive addresses. Using the packed packing mode, the array indices are packed to eliminate gaps in the memory. In the aligned packing mode, the array indices are generally shifted by a power-of-two number. The aligned packing mode typically reduces the amount of hardware needed for memory address calculation (for example, by eliminating an adder or subtractor), but usually requires more memory.
After the designer designates the type of memory and packing method in the HDL source code (using pragma statements or other directives), the designer runs the source code through the synthesis tool. The synthesis tool generates a report that the designer can use to analyze the performance of the circuit. For example, the user can examine the speed and area of the circuit to determine whether the current memory allocation is acceptable. If the memory allocation is not acceptable, the designer must return to an editor, re-edit the source code to change the memory allocation, and run the source code through the synthesis tool again. Such a technique for modifying the memory allocation is time consuming and inefficient. Moreover, the designer cannot easily visualize how the memory is allocated while modifying the source code.
It is desirable, therefore, to provide a synthesis tool that allows a designer to modify memory resources more quickly and simply. It is further desirable to allow a designer to readily visualize a memory map of the circuit after the designer allocates memory resources.
SUMMARY
The present invention allows a designer to interactively change the memory allocation in an integrated circuit design without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the memory allocation easily and see the results of the new allocation without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view a memory map of the circuit to better determine whether the memory allocation is acceptable. Additionally, the designer can execute an area-versus-speed analysis, and, if the analysis is not satisfactory, the designer can further modify the memory allocation using the GUI.
In one aspect, a source code file having a description of the hardware is read into a database within the synthesis tool. The synthesis tool analyzes the source code file and generates a data structure associated with the source code file. The designer can then invoke a GUI that lists the variables from the source code, together with the size of the variables, current memory allocation for the variables, and packing mode. The designer can then interactively create new memory resources and drag and drop the variables onto the memory resources to allocate the memory interactively and without having to change the source code file.
In another aspect, the designer can interactively change other parameters associated with the memory resources, such as the memory type, packing mode, etc. Thus, rather than having to change the source code file, the designer can select a memory resource in the GUI and change these memory parameters interactively and dynamically.
In yet another aspect, the designer can view a graphical representation of a memory map that illustrates the mapping of variables to memory addresses. If the designer is dissatisfied with the memory layout, the designer can interactively modify the memory allocation to find a more satisfactory solution.
Further features and advantages of the invention will become apparent with reference to the following detailed description and accompanying drawings.


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Elliott, John P.,Understanding Behavioral Synthesis: A Practical Guide to High-Level Design, Ch. 2, pp. 5-23, and Ch. 9, pp. 155-172, Kluwer Academic Publishers, 1999.

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