Interactive loop configuration in a behavioral synthesis tool

Details Interactive loop configuration in a behavioral synthesis tool Interactive loop configuration in a behavioral synthesis tool

2002-04-19

2004-11-09

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06817007

ABSTRACT:

FIELD
The present invention relates generally to behavioral synthesis tools for creating integrated circuits, and more particularly relates to behavioral synthesis tools that allow for interactive loop manipulation during the design of integrated circuits.
BACKGROUND
The design of complex computer hardware no longer begins with a circuit diagram. Instead, it begins with a software program that describes the behavior or functionality of a circuit. This software program is written in a hardware description language (HDL) that defines an algorithm to be performed with limited implementation details. Designers direct behavioral synthesis tools to generate alternate architectures by modifying constraints (such as clock period, number and type of data path elements, and desired number of clock cycles). Behavioral synthesis tools convert the HDL program into a register transfer level (RTL) description. The RTL description is used to ultimately generate a netlist that includes a list of components in the circuit and the interconnections between the components. This netlist is used to create the physical integrated circuit.
In HDL source code, loops may be used to conveniently describe the behavior of a hardware circuit. For example, “WHILE” loops, “FOR” loops, and “INFINITE” loops may be used in HDL code that are similar to loop declarations used in other programming languages. An INFINITE loop is a loop that does not describe any conditions for exiting the loop in its declaration. By contrast, FOR and WHILE loops describe in their declaration the conditions under which the loop is terminated.
Loop unrolling is a transformation that may be applied to the loop construct. When a loop is unrolled, the statements inside the loop are copied as many times as the loop is unrolled. When the loop is unrolled, the control structure of the loop is modified to maintain the same functionality. Loops may be either completely unrolled or partially unrolled. For each copy of the loop statements, the iteration variable is replaced with the appropriate constant for that iteration of the loop. For example, the FOR loop in table 1 can be unrolled to the format of table 2
TABLE 1
FOR I IN 0 to 7 LOOP
 tmp := tmp + s(I);
End LOOP;
TABLE 2
tmp := tmp + s(0);
tmp := tmp + s(1);
tmp := tmp + s(2);
tmp := tmp + s(3);
tmp := tmp + s(4);
tmp := tmp + s(5);
tmp := tmp + s(6);
tmp := tmp + s(7);
Behavioral synthesis tools also support pipelining techniques to improve the throughput of synthesized designs. Pipelining can be used in designs to reduce the latency of a design or to reduce the total area of the components used in the design. Loop pipelining is a feature of behavioral synthesis tools that allows one iteration of a loop to begin before the previous iteration is completed. Loop pipelining can be used to increase the throughput of a loop, but often at the expense of additional component area. A pipelined component is usually created from a combinational component with similar functionality by dividing the logic of the combinational component into multiple stages and placing registers between the stages to hold intermediate results. Pipelined components are characterized by their initialization interval, latency, output delay, and minimum clock period. The initialization interval of a pipelined component specifies the rate at which the component can begin processing new input data. Most pipelined components have an initialization interval of 1, which means that the component can begin processing new input data every clock cycle. The latency of a pipelined component specifies the number of clock cycles it takes to compute output values. This value is one less than the number of stages in the pipelined component. The output delay of the pipelined component is the combinational delay through the last stage of the pipe. If the pipelined component registers its outputs, the value of the output delay is just the clock-to-output delay of the register. The minimum clock period is determined by the longest path between registers within the component. If the clock period were shorter than this value, the component would be unable to correctly capture intermediate values.
Some behavioral synthesis tools unroll loops by default and set default values for loop pipelining. However, the designer also can manipulate loop unrolling and pipelining through the use of HDL attributes or directives. For example, Synopsis® tools use a “pragma” statement in the source code to allow the designer to manipulate loops. Those skilled in the art recognize that loop unrolling and loop pipelining are mutually exclusive.
After the designer designates the loop unrolling and loop pipelining in the HDL source code (using pragma statements or other directives), the designer runs the source code through the synthesis tool. The synthesis tool generates a report that the designer can use to analyze the performance of the circuit. For example, the user can examine the speed and area of the circuit to determine whether the loop unrolling and pipelining is acceptable. If the loop configuration is unacceptable, the designer must return to an editor, re-edit the source code to change the loop configurations, and run the source code through the synthesis tool again. Such a technique for modifying the loops is time consuming and inefficient. Moreover, the designer cannot easily visualize the effects of the loop configuration the while modifying the source code.
It is desirable, therefore, to provide a synthesis tool that allows a designer to manipulate loops more quickly and simply. It is further desirable to allow a designer to readily visualize the effects of the loop configuration.
SUMMARY
The present invention allows a designer to interactively configure loops (via unrolling or pipelining) in an integrated circuit design without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the loop configurations easily and see the results of the modification without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view an area-versus-speed chart of the circuit to better determine whether the loop configurations are acceptable.
In one aspect, a source code file having a description of the hardware is read into a database within the synthesis tool. The synthesis tool analyzes the source code file and generates a data structure associated with the source code file. The designer can then invoke a GUI that lists the loops from the source code in a hierarchical fashion, together with the default values of the loop frequency, loop unrolling, and pipelining. The designer can then interactively modify the loops by changing the loop unrolling, and/or pipelining without having to change the source code file.
Further features and advantages of the invention will become apparent with reference to the following detailed description and accompanying drawings.


REFERENCES:
patent: 6691301 (2004-02-01), Bowen
patent: 2003/0105620 (2003-06-01), Bowen
U.S. patent application Ser. No. 09/839,376, Prakash et al., filed Apr. 20, 2001.
U.S. patent application Ser. No. 09/919,650, Gutberlet et al., filed Jul. 31, 2001.
U.S. patent application Ser. No. 09/957,442, Waters et al., filed Sep. 18, 2001.
U.S. patent application Ser. No. 60/362,679, Prakash et al., filed Mar. 8, 2002.
U.S. patent application Ser. No. 10/126,913, Bowyer et al., filed Apr. 19, 2002.
“Loops”,Understanding Behavioral Synthesis(A Practical Guide to High-Level Design), by John P. Elliott, Chapter 6, pp. 77-103 (1999).
“Pipelining”,Understanding Behavioral Synthesis(A Practical Guide to High-Level Design), by John P. Elliott, Chapter 8, pp. 137-154 (1999).
“Handel-C: Software Compiled System Design,” , http://www.celoxica.com/methodology/handelc.asp; 2 pages; website visited on Dec. 10, 2003.

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