Interactive dubug tool for programmable circuits

Details Interactive dubug tool for programmable circuits Interactive dubug tool for programmable circuits

1997-11-24

2001-04-03

Wright, Norman (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S038110, C714S031000

Reexamination Certificate

active

06212650

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to graphical methods for debugging electronic circuits. More particularly, the invention relates to an interactive graphical software tool for probing and stimulating circuits in programmable logic devices such as field programmable gate arrays (FPGAs).
2. Description of the Background Art
Electronic systems including programmable logic devices have been increasing in popularity and are now common. However, while many hardware platforms have been built, software support for testing and debugging the programmable devices in these systems has lagged. In the area of software support, the emphasis has been on design tools. By contrast, few debug environments for the programmable devices in these logic systems have been developed. While the programmable devices are typically thoroughly tested prior to being included in the systems, it has heretofore been difficult to completely test configured (programmed) devices within the system. The post-programming configuration data must be inferred from the behavior of the programmed device, or from viewing the states of known “probe points” on the device.
Some debug tools for programmable logic systems are known. These tools typically provide one or both of two types of functionality, symbolic debug and state readback display. Symbolic debug provides a table of variable or signal names whose value changes over time. The data may be displayed as a table or as a waveform, similar to a hardware logic analyzer. The variable or signal names correspond to probe points. One such debug tool, the “Xilinx Hardware Debugger”, is described in the “Hardware Debugger Reference/User Guide” (hereinafter referred to as the “Xilinx Hardware Debugger Guide”), published October, 1995, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which is incorporated herein by reference in its entirety. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) As shown on page 1-2 of the Xilinx Hardware Debugger Guide, the probe points are limited to Configurable Logic Block (CLB) outputs, I/O Block (IOB) outputs, and RAM/ROM outputs for the Xilinx XC4000 FGPA device. The symbolic debug process is described in Chapter 6 of the Xilinx Hardware Debugger Guide.
State readback display provides the complete state of the supported latched signals of the FPGA device, typically the outputs of each flip-flop or CLB. Patrice Bertin and Hervi Touati reference a software programming environment called “SHOWRB” that can display the state of each FPGA flip-flop in pages 133-138 of “IEEE Workshop on FPGAs for Custom Computing Machines”, edited by Duncan A. Buell and Kenneth L. Pocek, published April, 1994 by the IEEE Computer Society Press, Los Alamitos, Calif., which pages are incorporated herein by reference.
When either symbolic debug or state readback display is used, the functionality of the configured device can be verified by watching the behavior of the displayed probe points in response to inputs applied to device input (or input/output) pads. The Xilinx Hardware Debugger supplies a limited number of input signals to the input/output (I/O) pins of the configured device: clocks, configuration input data (as part of a configuration bitstream), configuration control signals, and a signal that triggers a configuration data readback sequence. (See pages 4-7 and 4-8 of the Xilinx Hardware Debugger Guide.) Other inputs can be externally generated and applied to other I/O pins.
The Xilinx Hardware Debugger also offers a means to verify that the configuration data loaded into the device matches the bitstream used to configure the device. As described on pages 5-5 and 5-6 of the Xilinx Hardware Debugger Guide, when the Verify command is issued, the number of verified bits is reported. The user must then check that the number of verified bits corresponds to the number of downloaded bits. If the numbers correspond, the configuration data matches the bitstream. If not, an error has occurred. The location of the error is not reported. The symbolic debug data, observed data about the behavior of the system, or other data must be used to track down the error. The resulting debug process can be time-consuming and laborious.
It is therefore desirable to have direct access to the configuration data of a configured device in order to more quickly and easily determine the source of an error in a configured device that is part of an electronic system. It is also desirable to simplify the debug process by providing the ability to apply stimulus to probe points distributed throughout the configured device, rather than to a set of I/O pins having limited functionality.
SUMMARY OF THE INVENTION
An interactive graphical software tool and method are provided that can be used to report the configuration data (i.e., the state of the various configuration bits) in a programmed device as well as to probe and stimulate circuits in the programmed device. A graphical or textual representation of the configuration data can be displayed. When used with a programmable device having addressable flip-flops, such as a member of the Xilinx XC6200 family, one embodiment of the invention can change the state of any addressable flip-flop in the configured device. Using this method, a wide variety of stimuli can be applied to any of a large number of points in the configured device, greatly simplifying the debug process.
The unique ability to display the configuration data read from the device has many applications. For example, this capability can facilitate the hardware testing of an FPGA and the location of errors. Configuration data can be written to the device, then read back from the configured device. The resulting information is not limited to “there is an error somewhere on the device”, as in the prior art, but provides means for directly verifying the nature and location of the error.
The ability to display the configuration data can also be used for debugging circuits implemented in the configured device, and therefore for debugging software that creates such circuits. In one embodiment, the information is displayed in a format that actually draws a picture of the logic implemented in a configured logic cell. For example, a logic cell configured as a NAND-gate driving a flip-flop is represented by a picture of a NAND-gate symbol (similar to a schematic symbol) with its output driving the data input of a flip-flop symbol. Circuit errors are easily detected. This aspect of the invention has particular relevance to a growing application of reconfigurable logic, the use of FPGAs as co-processors. In this application, a microprocessor programs all or a portion of an FPGA to perform subroutines. The subroutine is typically changed frequently to meet the requirements of the software program running on the microprocessor; therefore the microprocessor is frequently “designing” new FPGA circuits on the fly. Testing the microprocessor functionality in this area is historically difficult, but the process is greatly simplified by applying the methods of the invention.
The graphical tool of the invention is preferably implemented using a high level programming language such as Java™ and features a graphical point and click user interface, remote access to hardware, and symbolic debug capability. (“Java” is a trademark of Sun Microsystems, Inc.) Therefore, the graphical, interactive software interface of the invention interacts directly with the electronic development system at the hardware level. In this respect the invention more closely resembles In-Circuit Emulators (ICEes) popular in microprocessor development environments than it resembles a software debugging environment. Because it operates primarily at the hardware level, the invention operates independently of other design tools or software packages. This independence enhances the portability of the invention.


REFERENCES:
patent: 5109353 (1992-04-01), Sample et al.

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