Interactive circuit assembly test/inspection scheduling

Details Interactive circuit assembly test/inspection scheduling Interactive circuit assembly test/inspection scheduling

2006-02-28

2006-02-28

Baderman, Scott (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C718S102000

Reexamination Certificate

active

07007206

ABSTRACT:
Systems and methods for scheduling circuit assemblies for inspection in an electronics manufacturing environment are provided. One embodiment comprises an interactive system for scheduling circuit assemblies for inspection. Briefly described, one such system comprises: a data structure residing in memory and comprising a plurality of data elements that define the order in which a plurality of circuit assemblies are scheduled to be inspected, each data element comprising a reference to one of the plurality of circuit assemblies; logic configured to control the manner in which the plurality of circuit assemblies are scheduled for inspection based on the data structure; and logic configured to enable a user to modify the data structure.

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patent: 2003/0139952 (2003-07-01), Lubash et al.
patent: 2004/0163241 (2004-08-01), White
patent: 11150352 (1999-06-01), None

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