Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-21
2004-09-21
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S303000, C257S304000, C257S311000
Reexamination Certificate
active
06794694
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuits, and more particularly to capacitors in integrated circuits.
2. Discussion of the Related Art
Many integrated circuits use on-chip capacitors. The on-chip capacitors are either located in trenches in semiconductor substrates or stacked above the semiconductor substrates.
Typically, the trench capacitors are made prior to finishing devices in the substrate. To withstand subsequent device finishing, the trench capacitors use materials tolerant of anneals used to finish devices. The tolerant materials include doped polysilicon, which is used for capacitor charge-storage electrodes, and silicon nitride and silicon dioxide, which are used for capacitor dielectrics.
Typically, the stacked capacitors are fabricated after finishing devices located in the substrate. Since the stacked capacitors do not have to tolerate the harsh anneals used to finish the devices in the substrate, the stacked capacitors are able to exploit fragile materials with better electrical properties. The fragile materials include new capacitor dielectrics and metal-based charge-storage electrode materials. The new dielectrics have higher dielectric constants than silicon dioxide or silicon nitride and thus, produce higher capacitances. The metal-based materials have lower resistances than doped polysilicon and thus, lower resistances of charge-storage electrodes and capacitor charge and discharge times.
Some stacked capacitors use both the new dielectrics and metal-based charge-storage electrode materials. Constructing these stacked capacitors requires several lithographic steps that use different masks. In one such step, a first mask is used to control an etch of a via in a dielectric layer. In another such step, a second mask is used to form a charge-storage electrode in the previously etched via. The use of several masks complicates construction of these stacked capacitors.
BRIEF SUMMARY OF THE INVENTION
In one aspect, the invention features an integrated circuit. The integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.
In another aspect, the invention features a process for forming an integrated circuit. The process includes providing a semiconductor substrate with semiconductor devices, forming a first wiring layer and a portion of a second wiring layer over the substrate, opening a window that is continuous through the first wiring layer and the portion of the second wiring layer, and forming a capacitor in the window. The capacitor has charge-storage electrodes that extend through the first wiring layer and the portion of the second wiring layer.
In another aspect, the invention features a process for fabricating an integrated circuit with embedded memory cells. The process includes providing a substrate with semiconductor devices for logic circuits and for DRAM cells in first and second physical regions, respectively, and fabricating a first and at least a portion of a second wiring layer over the substrate. The interconnect wire is not present in the wiring layers over the second regions. The process also includes fabricating a capacitor with metal-based charge-storage electrodes that extend through the thickness of the first wiring layer and the portion of the second wiring layer over the second regions.
REFERENCES:
patent: 5471418 (1995-11-01), Tanigawa
patent: 6078072 (2000-06-01), Okudaira et al.
patent: 6180976 (2001-01-01), Roy
patent: 6194757 (2001-02-01), Shinkawata
patent: 6265778 (2001-07-01), Tottori
patent: 6281535 (2001-08-01), Ma et al.
Diodato Philip W
Liu Chun-Ting
Liu Ruichen
Agere Systems Inc.
Botos Richard J.
Jackson Jerome
Nguyen Joseph
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