Boots – shoes – and leggings
Patent
1992-11-02
1995-10-17
Kriess, Kevin A.
Boots, shoes, and leggings
364228, 364229, 364230, 364240, 364251, 3642511, 3642513, 3642551, 3642592, 3642613, 364DIG1, 39520008, 395827, 395847, 395650, G06F 300, G06F 1516
Patent
active
054598362
ABSTRACT:
A message transfer system between multiple processors in a network. Each processor includes an interprocessor communications (IPC) hardware unit having an unique address count. An address count generator in a designated IPC hardware unit generates a sequence of binary count numbers such that when the generated count number matches the address of the IPC hardware unit, then that particular hardware unit and its associated processor are granted a time period of bus access for sending messages on the IPC network bus to other processors. Messages on the IPC network bus can be received by an IPC hardware unit at any time irrespective of the generated count number. Any sending processor that has bus access can concurrently provide multiple messages where each of the multiple messages is directed to each particular processor for reception. Thus one sender, with bus access, can communicate with multiple receivers during its transmission onto the IPC network bus connecting the processors.
REFERENCES:
patent: 4161786 (1979-07-01), Hopkins et al.
patent: 4387425 (1983-06-01), El-Gohary
patent: 4499538 (1985-02-01), Finger et al.
patent: 4816990 (1989-03-01), Williams
Barajas Saul
Watson Leland E.
Whittaker Bruce E.
Axenfeld Robert R.
Chavis John Q.
Kozak Alfred W.
Kriess Kevin A.
Starr Mark T.
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