Inter-procedural allocation of stacked registers for a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring

Reexamination Certificate

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C711S100000, C711S154000, C711S156000, C711S165000, C712S202000, C712S228000

Reexamination Certificate

active

07120775

ABSTRACT:
A method for an allocation of stacked registers for Intel's Itanium® processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a plurality of procedures. In step II, the disclosed method performs an inter-procedural analysis to assign quota of stacked register usage to every procedure. In step III, each procedure is allocated stacked register usage based on the quota assignments of step II.

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L. Yang, S. Chan, G.R. Gao, R. Ju, G.-Y. Lueh, and Z. Zhang, “Inter-procedural Stacked Register Allocation for Itanium-like Architecture,” Proc. of 2003 Int'l Conference on Supercomputing (ICS), pp. 215-225, Jun. 2003.

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