Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-15
2001-12-04
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06327692
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to designing integrated circuits, and more particularly to a methodology for designing application specific integrated circuits (ASICs) that places buffers between modules of an ASIC so that design changes to an upstream module do not readily propagate to downstream modules and cause design changes to the downstream modules.
2. Related Art
Circuit design is presently accomplished primarily through the use of computer aided design (CAD) tools, which take as input a circuit specification and automatically generate and simulate circuit descriptions suitable for implementation. One type of circuit commonly designed using CAD tools is an application specific integrated circuit (ASIC). ASICs are often very complex. Consequently, design of an AGIC is typically accomplished by dividing an ASIC into a plurality of modules, which are designed separately-often by different designers. This process of dividing an ASIC into modules has a number of advantages. It is more efficient computationally to synthesize and test modules of a circuit independently first, so that module designs are stabilized before synthesizing and testing a complete circuit. Furthermore, breaking up a circuit into separately designed modules allows a circuit to be designed by a group of designers working somewhat independently on separate modules.
However, this process of dividing a circuit gives rise to a number of problems in ultimately recombining the modules into a circuit. For example, a change to an input signal of a module may cause changes to characteristics of an output signal from the module. This may cause the input to a downstream module to change, which may cause an output of the downstream module to change, and so on, until the changes propagate through many modules in the circuit. Each time an output changes, the circuit may have to be re-synthesized and/or re-tested, which can be a very time-consuming process. Consequently, this potential rippling of changes through a circuit can greatly increase the time required to design a circuit, and may ultimately lead to increased costs for the circuit.
Furthermore, if an output signal from a module may be affected feeds back into the module, the signal that feeds back into the module may be affected by downstream loads on the output signal. Consequently, downstream connections of the output signal may affect the timing of signals within the module, which may trigger changes in the design of the module.
Additionally, when modules are integrated together, signals are often not routed optimally because output drivers are placed at various locations during the design of a module without regard for the effect of such placement on the optimal routing of signals between modules.
What is needed is a method for designing a circuit that limits the ability of design tools to automatically change the characteristics of signals travelling between modules, so that design changes to a module do not needlessly create design changes in downstream modules of a circuit.
Additionally, what is needed is a method for designing a circuit that insulates output signals that feed back into a module from the effects of loads placed on the output signals outside the module.
Furthermore, what is needed is a method for designing a circuit that carefully locates output drivers for modules of the circuit, so that signals are more optimally routed between modules of a circuit.
SUMMARY
One embodiment of the present invention provides a method for designing a circuit that limits the impact of design changes within a module of a circuit to the characteristics of signals flowing between modules of the circuit. This method operates by dividing the circuit into a plurality of circuit modules, and defining a plurality of interface modules located between the plurality of circuit modules. These interface modules include drivers coupled between upstream circuit module outputs and downstream circuit module inputs, so as to isolate the downstream circuit module inputs from the upstream circuit module outputs. Next, the circuit modules and interface modules are designed, and a synthesized circuit is ultimately generated from the designs. This synthesized circuit is then verified for characteristics such as timing. If it fails to verify, design changes are made. In one embodiment, these design changes include: re-specifying constraints for modules, re-generating designs for modules, and re-dividing the circuit into modules. By locating drivers within separate interface modules, the drive strengths of the drivers can be more easily specified. Furthermore, by locating the drivers at particular positions within an interface module, the signals flowing through the drivers can be guided to flow in such a way as to route signals along shorter, more optimal pathways between modules.
In one embodiment of the present invention, the act of generating a synthesized circuit from the designs includes: generating synthesized modules from the designs; and generating a synthesized circuit from the synthesized modules. In a variation on this embodiment, the method includes verifying functionality of the circuit modules from the design specifications before generating the synthesized modules.
In another embodiment of the present invention, the act of creating designs includes: writing design specifications for circuit modules and interface modules; and specifying constraints for the circuit modules and interface modules. In a variation on this embodiment, the act of specifying constraints includes specifying input and output delays for a module. In another variation on this embodiment, the act of specifying constraints includes specifying load values for outputs from a module.
In another embodiment, the act of defining interface modules includes defining a first interface module as a ring surrounding a first circuit module, so that inputs and/or outputs from the first circuit module pass through the first interface module. In a variation on this embodiment, the ring includes drivers configured so that outputs passing through the ring pass through the drivers. In another variation, a first set of outputs from the first circuit module pass through drivers in the first interface module, and a second set of outputs from the first circuit module pass straight through the first interface module without passing through intervening drivers or other gates in the first interface module. In yet another variation, an interface module takes the form of a ring surrounding a group of circuit modules so that inputs and/or outputs from the group of circuit modules pass through the ring.
In another embodiment of the present invention, the act of verifying the synthesized circuit includes verifying timing for the synthesized circuit.
In another embodiment of the present invention, the method includes generating a placement and a routing for the synthesized circuit.
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Micro)n Technology, Inc.
Park Vaughan & Fleming LLP
Siek Vuthe
Smith Matthew
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