Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-12-01
2004-01-13
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C713S401000
Reexamination Certificate
active
06678783
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an inter-device coupler which arbitrates data transfer between devices operating at different speeds, more particularly relates to a coupler of an arithmetic logical unit (ALU) and a memory for a memory closely coupled with an ALU.
2. Description of the Related Art
In a processor as a coupler for closely coupling an ALU and a memory, the write and read speed of the memory often becomes a bottleneck.
Therefore, in the related art, the practice has been to make the operating speed of the ALU twice the memory access speed, provide a coupler between the ALU and memory, perform serial-parallel conversion and parallel-serial conversion, and prevent a fall in the bandwidth even if the access speed of the memory is low.
FIG. 1
is a circuit diagram of an example of the configuration of a coupler of an ALU and a memory of the related art.
The coupler
10
comprises, as shown in
FIG. 1
, positive-edge D-type flip-flops
11
,
12
,
13
,
14
, and
19
, memories
15
and
16
, negative-edge D-type flip flops
17
and
18
, and a two-input one-output selector
20
. Reference number
21
indicates the ALU.
In the coupler
10
, a clock signal CK
1
is supplied to the flip-flops
11
,
12
, and
19
, while a clock signal CK
2
is supplied to the flip-flops
13
,
14
,
17
, and
18
.
An output signal ALUOT of the ALU
21
is supplied to an input D of the flip-flop
11
. An output signal OTD
1
from the output Q of the flip-flop
11
is supplied to inputs of the flip-flops
12
and
13
, respectively, while an output signal OTD
0
from an output Q of the flip-flop
12
is supplied to an input D of the flip-flop
14
.
The output signals OT
1
and OT
0
from the outputs Q from the flip-flops
13
and
14
are respectively supplied to write ports of memories
15
and
16
, while read signals IN
1
and IN
0
from read ports of the memories
15
and
16
are supplied to inputs D of the flip-flops
17
and
18
.
An output signal IND
0
from an output Q of the flip-flop
18
is supplied to a port A of the selector, an output signal IND
1
from an output Q of the flip-flop
17
is supplied to an input D of the flip-flop
19
, and an output signal IND
2
from an output Q of the flip-flop
19
is supplied to a port B of the selector
20
. An output signal from the selector
20
becomes an input signal ALUIN of the ALU
21
. A selection signal of the selector
20
is made OSEL.
Assuming that the CK
1
is a normal clock signal, the CK
2
is a clock obtained by frequency-division of CK
1
.
The memories
15
and
16
are written into at rising edge of the clock signal CK
2
and read from at a trailing edge of the clock signal CK
2
. It takes three cycles of the clock signal CK
1
from the writing to reading due to the nature of the memories.
Next, an operation of the coupler
10
of an ALU and a memory of the related art will be explained with reference to timing charts of
FIGS. 2A
to
2
N.
FIGS. 2A
to
2
N are timing charts of the case when immediately reading data written in a memory and transferring it to the ALU.
First, as shown in
FIG. 2C
, data streams n
0
, n
1
, n
2
, n
3
. . . are output as a signal ALUOT from the ALU
21
.
As shown in
FIGS. 2D and 2E
, the n
0
, n
1
, n
2
, n
3
. . . are output respectively delayed by one cycle and two cycles of the clock signal CK
1
from the flip-flops
11
and
12
.
At this time, since the phase relationship of the clock signals CK
1
and CK
2
is set as shown in
FIGS. 2A and 2B
, outputs from the flip-flops
13
and
14
are delayed by four cycles from the input of n
0
to the flip-flop
11
.
The data is written in the memories
15
and
16
and sent to the flip-flops
17
and
18
after three cycles.
An output of the flip-flop
17
is delayed exactly by one cycle in the flip-flop
19
and output to the port B of the selector
20
.
By changing the selection signal OSEL of the selector
20
by the timing shown in
FIG. 2M
, data of n
0
, n
1
, n
2
. . . from the selector
20
is output from the ALU
21
.
Summarizing the problem to be solved by the invention, in the coupler
10
of the related art, a delay of 7 cycles was required between writing data of the ALU
11
in a memory and reading it again from the memory.
Accordingly, in the coupler
10
of an ALU and memory of the related art, the delay becomes long when temporarily writing output data from the ALU
21
and using the same immediately after the writing. There is a period when no computations are possible until the read data becomes usable in the ALU
21
.
The reason why the delay becomes 7 cycles is that two cycles are needed for changing a clock from CK
1
to CK
2
, three cycles for writing and reading to and from the memory, and two cycles for switching the clock from CK
2
to CK
1
.
One method for solving this problem is to provide more registers inside the ALU, but the connections to the registers become complex, the control circuit also becomes complex, and furthermore the power consumption in the clock system increases because it has to be always operated by the CK
1
clock.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an inter-device coupler capable of giving any delay to output data of an ALU and outputting the result as input data of the ALU with a simple configuration and without increasing the power consumption.
To attain the above object, according to a first aspect of the present invention, there is provided an inter-device coupler for arbitrating data transfer between an ALU and a memory operating at different speeds, comprising a first input circuit operating at the same speed as the ALU and receiving as input and outputting output data of the ALU; a second input circuit operating at the same speed as the memory and receiving as input and outputting output data of the first input circuit to the memory; a first output circuit operating at the same speed as the memory and receiving as input and outputting read data of the memory; a second output circuit operating at the same speed as the ALU and outputting input data to the ALU; and a path selector for inputting at least one of the output data of the first input circuit or the output data of the first output circuit to the second output circuit in accordance with a value of a path selection signal.
Preferably, the path selector inputs the output data of the first input circuit, the output data of the second input circuit, or the output data of the first output circuit to the second output circuit in accordance with the value of the path selection signal.
According to a second aspect of the present invention, there is provided an inter-device coupler for arbitrating data transfer between an ALU and a memory operating at different speeds, comprising a first input circuit operating at the same speed as the ALU and receiving as input and outputting output data of the ALU; a second input circuit operating at the same speed as the memory and receiving as input and outputting output data of the first input circuit to the memory; a first output circuit operating at the same speed as the memory and receiving as input and outputting read data of the memory; a selection circuit operating at the same speed as the memory, comprising a first input and a second input, and selecting an input signal for the first input or an input signal for the second input and outputting the same to the ALU in accordance with an output selection signal; a second output circuit operating at the same speed as the ALU and outputting input data to the ALU; and a path selector for inputting at least one of the output data of the first input circuit or the output data of the first output circuit to the first input of the selection circuit or the second output circuit in accordance with a value of a path selection signal.
Preferably, the path selector inputs the output data of the first input circuit, the output data of the second input circuit, or the output data of the first output circuit to the first input of the selection circuit or the second ou
Auve Glenn A.
Frommer William S.
Frommer & Lawrence & Haug LLP
Sony Corporation
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