Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
2007-07-19
2011-11-01
Abraham, Esaw (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
C714S758000, C714S807000
Reexamination Certificate
active
08051338
ABSTRACT:
An apparatus includes a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes lane includes the SerDes circuit pair coupled by a communications medium. The LCB includes an error tracking circuit and a controller. The controller includes an error recovery module configured to retry a data communication when an error is detected and deactivate the SerDes lane when a rate of errors on the SerDes lane exceeds a threshold error rate value. Other devices, systems, and methods are disclosed.
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Abraham Esaw
Cray Inc.
Schwegman Lundberg & Woessner, P.A.
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