Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-20
2001-05-08
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S370000, C257S329000, C257S335000
Reexamination Certificate
active
06229179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to an intelligent power integrated circuit having a power device and a control device formed on the same substrate, and to a method for manufacturing the same.
2. Description of the Related Art
An intelligent power integrated circuit having a vertical double diffusion MOS (VDMOS) as an output device, in which a power device and a control device controlling the same are formed on the same substrate, is used for an application for controlling solenoid. The power integrated circuit usually employs the SOI structure to electrically insulate the power device from the control device. However, a buried oxide layer should be partially formed such that drain current of the VDMOS can vertically flow, so that it is difficult to manufacture the SOI structure.
Much research for realizing an intelligent power integrated circuit is currently being conducted. Here, silicon direct bonding technology by which the intelligent power integrated circuit having partially bonded SOI substrates can be obtained will be described (from “Partially Bonded SOI Substrates for Intelligent Power Ies”, Solid State Device and Materials, 1995, pp. 848-850, Hiroaki Kikuchi and Kenichi Arai).
FIGS. 1A through 1E
are sectional views for illustrating a method for manufacturing a conventional intelligent power integrated circuit forming a power device and a control device on the same substrate.
A buried oxide layer
12
is formed in a control device portion of a first wafer
10
of N
−
-type in a trench, as illustrated in
FIG. 1A
, formed by etching which is etched with an HF solution until a recess portion
14
of approximately 0.1 &mgr;m is formed (FIG.
1
B).
Subsequently, the first wafer
10
having the recess portion
14
and a second wafer
16
of N
+
-type are processed in a SCI solution to remove impurity particles from a bonding surface. During the above process, native oxides layer formed on the two wafers strengthen the bonding strength, so that the bond does not separate. Then, the first wafer
10
having the recess portion
14
and the second wafer
16
are bonded at a room temperature. Subsequently, an annealing process is performed to strengthen the bonding strength of the bonded wafers. As a result, a gap G is formed between the buried oxide layer
12
and the second wafer
16
of N
+
-type(FIG.
1
C).
Then, the first wafer
10
of N
−
-type is polished to form an active layer. At this time, the thickness of the active layer, which is the thickness of the polished first wafer, is chosen to achieve a desired breakdown voltage between a source of a VDMOS and a drain thereof to be formed (FIG.
1
D). Subsequently, a control device is formed in an active layer (a control device portion) on the buried oxide layer
12
and the gap G, and the VDMOS of a power device is formed in other regions, i.e., a power device portion (FIG.
1
E).
The method for manufacturing an intelligent power integrated circuit IC using the above-described direct bonding technology is for manufacturing the SOI substrate partially formed on the second wafer
16
of N
+
-type of a high concentration. At this time, the control device is formed on the SOI structure, and a power device of VDMOS is formed in a region other than the SOI structure. That is, the buried oxide layer is partially formed on the first wafer, which is bonded to the second wafer using the silicon direct technology, to thereby easily manufacture the intelligent power integrated circuit in which the VDMOS of the power device and the control device are formed on the same wafer, i.e., on the second wafer
16
of N
+
-type.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide an intelligent power integrated circuit in which an insulated gate bipolar transistor having a low on-state voltage drop low R
ds
(on) and a rapid switching characteristic and a control device controlling the same are formed on the same substrate.
It is another objective of the present invention to provide a method for manufacturing the intelligent power integrated circuit.
Accordingly, to achieve the first objective, an intelligent power integrated circuit according to the present invention includes a handling substrate of a first conductivity type having a second buffer layer of a concentration which is higher than that of the handling substrate around the surface of the handling substrate contacting the substrate for a power device, a substrate for a power device of a second conductivity type where a first buffer layer of a concentration higher than that of the handling substrate is formed around a surface contacting with the handling substrate, a substrate for a control device formed on an insulating layer partially formed on the substrate for a power device, a control device formed on the substrate for a control device, a power device such as an insulated gate bipolar transistor (IGBT) vertically formed through the substrate for a power device and the handling substrate, and an insulating wall for preventing a power device formed on the substrate for a power device from being electrically connected to a control device formed in the substrate for a control device formed on the side wall of the substrate for a control device formed on an insulating layer partially formed on the substrate for a power device.
The handling substrate is a substrate doped with a high concentration P
−
-type impurity, and the substrate for a power device is a substrate doped with a low concentration N-type impurity, and the first buffer layer is a layer in which an N
−
-type impurity is doped with a concentration higher than that of the substrate for a power device, and the second buffer layer is a layer in which a P-type impurity is doped with a concentration higher than that of the handling substrate.
To achieve the second objective, a method for manufacturing an intelligent power integrated circuit according to one embodiment of the present invention includes the steps of: (a) bonding a substrate for a power device of a second conductivity type on a surface, of which a first buffer layer is formed, to a handling substrate of a first conductivity type, such that the first buffer layer contacts with the handling substrate, and then annealing the bonded substrate at approximately 1,150° C. to increase the bonding strength; (b) controlling the thickness of the substrate for a power device according to a desired breakdown voltage of a power device to be formed by etching such as wrapping or chemical mechanical polishing, and then forming an insulating layer as thick as electrical separation between the substrate for a power device and a substrate for a control device to be formed e.g., 1 &mgr;m~3 &mgr;m; (c) bonding a substrate for a control device on the insulating layer, and then annealing the bonded substrate at 1,100° C. to increase the bonding strength between the substrate for a control device and the insulating layer; (d) etching the substrate for a control device and the insulating layer stacked in the power device portion to thereby leave a pattern where the substrate for a control device and the insulating layer are stacked in the control device portion; and (e) forming a control device in the substrate for a control device, and a power device such as an insulated gate bipolar transistor (IGBT) in a substrate for a power device exposed by etching of step (d).
The handling substrate having a surface on which a second buffer layer is formed, is formed by steps of providing a handling substrate having the crystallization direction of (100) and a resistivity of 0.01 &OHgr;-cm in the CZ manner, injecting boron(B) ions with a dose of 1×10
15
~5×10
15
ion/cm
2
, and annealing the handling substrate where ions are injected at approximately 1,150° C. to form the second buffer layer, and the substrate for a power device having a surface on which a first buffer laye
Jang Hyeong-Woo
Jang Sin-Kook
Song Chang-Sub
Fairchild Korea Semiconductor Ltd.
Fenty Jesse A.
Lee Eddie C.
Rothwell Figg Ernst & Manbeck
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