Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-10-07
2003-06-17
Thai, Xuan M. (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S311000, C710S312000, C710S313000
Reexamination Certificate
active
06581129
ABSTRACT:
BACKGROUND
1. Field of the Present Invention
The present invention generally relates to the field of input/output (I/O) busses and more particularly to a system for integrating PCI-X and PCI compatible devices to achieve optimal performance.
2. History of Related Art
In the field of microprocessors based data processing systems, the use of industry standard I/O busses to improve the performance and expand the capabilities of data processing systems is well known. Standardized I/O busses provide a mechanism for connecting a wide variety of peripheral devices to the host bus of a data processing system. Peripheral devices may include, for example, high speed network adapters, hard-disk controllers, graphics adapters, audio adapters, and a variety of other devices. Among the most prevalent of the industry standard I/O busses is the Peripheral Component Interface (PCI) bus. The PCI bus has evolved over the years from revision 2.0 introduced in 1992 operating at a bus frequency of 33 MHz, to revision 2.1 introduced in 1995 with a maximum bus frequency of 66 MHz, to revision 2.2 introduced in 1998 and incorporating features such as message interrupts. Complete documentation of the PCI Local Bus Specification Rev. 2.2 is available from the PCI special interest group, 2575 N. E. Kathryn #17, Hillsboro, Oreg. 97124 (website www.pcisig.com). More recently, the PCI-X Addendum to Local Bus Specification Rev. 2.2 has been proposed as a means for further improving the performance of PCI busses. The PCI-X Addendum incorporates registered transactions that improve performance by permitting a PCI-X compatible bridge or I/O adapter to make decisions on every other clock cycle. For complete PCI-X documentation, the reader is referred to the PCI-X Addendum 1.0 Specification Review Draft available from the PCI special interest group.
Maintaining compatibility with the extremely large installed base of PCI compatible devices requires PCI-X bridges to be able to operate in either PCI-X mode or PCI mode. More specifically, a PCI-X bridge must be able to accommodate any combination of PCI and PCI-X operations on either of its interfaces (i.e., PCI-to-PCI-X, PCI-to-PCI, PCI-X-to-PCI-X and PCIX-to-PCI). If any I/O device or adapter on an I/O bus is operating in PCI mode, then the bus to which the PCI device is connected must operate in PCI mode as well thereby forcing all devices on the bus to assume PCI mode operation. Thus, a single adapter or device operating in PCI mode forces every other device on the same bus to operate in PCI mode as well.
A PCI-X bridge connected between a secondary bus operating in PCI mode and a primary bus operating in PCI-X mode must convert PCI commands issued by PCI mode adapters on the secondary bus to PCI-X commands that are forwarded to the host bridge over the primary bus. The conversion of some PCI commands to PCI-X commands can, in some cases, actually result in degraded performance of the PCI mode bus. When a high performance PCI adapter is performing sequential burst reads using PCI read multiple requests, for example, a PCI mode host bridge does predictive read ahead that stores multiple lines of data in a coherent cache such that, when the requesting adapter or bridge later issues the next sequential read (or read multiple) request, the host bridge does not have to go all the way back to system memory to get the next block of sequential data. In this manner, the predictive pre-fetching of data reduces memory latency, and reduces bandwidth consumption of the improved host bus performance. Thus, in a PCI environment, the PCI read multiple operation provides a hint or suggestion to the PCI host bridge to perform pre-fetching of information because the read multiple operation, by its definition, informs the host bridge that the requesting adapter will be back for additional data in the near future. Unfortunately, when converting a PCI read multiple request to a PCI-X compatible operation, this suggestion to perform predictive read ahead is lost. More specifically, the PCI read multiple request is converted to a PCI-X split read request in the form of a byte count read operation on the PCI-X side of the bridge. When a PCI-X host bridge detects a PCI-X byte count read operation the conventional PCI-X host bridge does not execute a predictive read ahead because the host bridge assumes that the byte counts indicates the precise quantity of data required by the requesting adapter. Thus, when the PCI adapter gets back on the bus requesting additional information, the PCI-X host bridge will not have pre-fetched any additional data and will, therefore, be required to access system memory resulting in potentially significant degradation of performance caused by excessive memory latency times. Therefore, it is desirable to implement a solution by which a PCI-X host bridge would recognize that certain PCI-X operations may have issued or originated from a PCI adapter performing a read multiple request and it would be further desirable if the bridge accommodated this possibility by acting in a manner as if it had received a multiple read request operation.
SUMMARY OF THE INVENTION
The above identified problems are in large part addressed by a PCI host bridge capable of determining whether a PCI-X operation might have originated as a PCI mode operation and, if so, generating a modified operation that requests more data than the PCI-X operation. The “excess” data fetched by the modified operation is then saved in anticipation of a subsequent request for the saved data. In this manner, the PCI host bridge improves system performance by reducing the time required to satisfy a read multiple request issued by a PCI mode adapter and by reducing host bus bandwidth consumption.
Broadly speaking, the invention contemplates a PCI host bridge and an associated I/O subsystem and method of operation. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI mode operation detection circuit. The host bus interface is suitable, for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI mode operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI mode adapter. In the preferred embodiment, the quantity of data requested by the modified operation and the quantity of data requested by the PCI-X operation differ. In one embodiment, the quantity of data requested by the modified operation exceeds the quantity of data requested by the PCI-X operation such that the modified operation results in a speculative pre-fetch of data. The PCI host bridge may further include storage buffers suitable for storing the speculatively pre-fetched data in anticipation of a subsequent request for the stored data. In one embodiment, the PCI-X operation comprises a request for data with a specified byte count. The specified byte count is equal to the number of bytes in a cache line of the data processing system. In one embodiment, the modified operation comprises a request for data with a byte count equal to a multiple of the byte count of the PCI-X operation. The PCI host bridge may further include a byte count register. In this embodiment, the specified byte count for detecting operations that may have issued from a PCI mode adapter equals the value stored in the byte count register. The PCI host bridge may further include a byte count multiplier register. In this embodiment, the byte count of the modified operation is determined by multiplying the value stored in the byte count register by the value stored in the multiplier.
REFERENCES:
patent: 5758166 (1998-05-01), Ajanovic
patent: 6170030 (2001-01-01), Bell
patent: 6175889 (2001-01-01), Olarig
patent: 6266731 (2001-07-01), Rile
Buckland Pat Allen
Moertl Daniel Frank
Neal Danny Marvin
Thurber Steven Mark
Willenborg Scott Michael
International Business Machines - Corporation
Lally Joseph P.
McBurney Mark E.
Thai Xuan M.
Vo Tim
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