Intelligent expansion ROM sharing bus subsystem

Details Intelligent expansion ROM sharing bus subsystem Intelligent expansion ROM sharing bus subsystem

2000-05-03

2003-03-04

Lefkowitz, Sumati (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S010000, C710S104000, C713S002000

Reexamination Certificate

active

06529989

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to intelligent bus subsystems, and more particularly to intelligent PCI bus subsystems that use expansion ROMs for boot-up and initialization.
2. Description of the Related Art
Modern computer systems typically employ buses to convey information between various parts in the computer systems. For example, computer systems generally include one or more buses to connect a central processing unit (CPU) to a main memory and input/output (I/O) devices for transferring data and control signals. Today, one of the most widely used buses is peripheral component interface (PCI) bus.
With the proliferation of I/O devices such as disk drives, tape drives, printers, scanners, and audio/video devices, the PCI bus is used to connect an increasing number of I/O devices. To accommodate the addition of more I/O devices, conventional computer systems typically provide one or more secondary PCI buses in addition to a primary PCI bus. An intelligent PCI subsystem provides a secondary PCI bus for this purpose. The I/O devices coupled to a secondary PCI on an intelligent PCI subsystem are typically not “visible” from the primary PCI bus. For communicating with devices on the primary PCI bus, each secondary PCI bus typically is coupled to the primary PCI bus through a PCI application bridge, which is often referred to as a non-transparent or opaque PCI bridge. A PCI application bridge and devices attached to the PCI bridge form a PCI subsystem.
Conventional PCI subsystems often require device specific software codes to be stored in an expansion ROM for use by a host processor from the primary PCI bus. In addition, local processors in intelligent PCI subsystems typically store device specific software codes in a separate expansion ROM connected to the associated local core logic chipsets for use by the local processors. Some examples of device specific codes are power-on self-test code, initialization code, interrupt service routine, BIOS routine, boot code, etc.
FIG. 1
illustrates a schematic block diagram of a conventional computer system
100
that uses a pair of expansion ROMs
132
and
134
for storing device specific software codes. In the computer system
100
, a primary PCI bus
104
is coupled to a host bus bridge
108
on the host side and to a PCI-to-PCI bridge
106
on the other. A host CPU
102
and a main memory
110
are coupled to the host bus bridge
108
. The host bus bridge
108
provides host chipset and functions as a memory controller in accessing the main memory
110
. In this configuration, the CPU
102
accesses the main memory
110
through the host bus bridge
108
to read or store information. The primary PCI bus
104
may also be coupled to other devices such as hard disk drives, audio/video devices, etc.
A secondary PCI bus
112
is coupled to the PCI-to-PCI bridge
106
, a SCSI adapter
114
, and a local CPU and chipset
116
. The SCSI adapter
114
is connected to a SCSI device
118
(e.g., SCSI drive, tape drive, CD drive, etc.) to provide additional functionality to the computer system
100
. The local CPU
116
provides additional processing capabilities and may be used, for example, as an I/O controller, audio/video processor, etc. In addition, other peripheral SCSI devices may also be attached to the secondary PCI bus
112
via SCSI adapter
114
or other SCSI adapters for providing additional functions.
The PCI-to-PCI bridge
106
is coupled between the primary PCI bus
104
and a secondary PCI bus
112
and functions to facilitate communication between the PCI devices coupled to the primary PCI bus
104
and the secondary PCI bus
112
. Specifically, the PCI-to-PCI bridge
106
includes a primary PCI interface
120
, a secondary PCI interface
122
, a bridge FIFO and controller
124
, an expansion ROM base address register
128
, and an expansion ROM interface logic and device pins
130
. The primary and secondary PCI interfaces
120
and
122
provide interface functions between the primary and secondary PCI buses
104
and
112
for communicating data and control signals. In particular, the primary PCI interface
120
interfaces with the primary PCI bus
104
on the host side while the secondary PCI interface
122
interface with the secondary PCI bus
112
.
Provided between the primary and secondary PCI buses
120
and
122
, the bridge and FIFO controller
124
receives transactions (e.g., requests or commands) on one bus as a slave and determines whether to pass the transaction to the other bus. When it determines that the transaction is to be passed on to the other bus, the bridge and FIFO controller
124
transmits the transaction onto the other bus as a master. For example, the bridge and FIFO controller
124
may receive and transmit a request between the PCI buses
104
and
112
via PCI interfaces
120
and
112
.
The PCI-to-PCI bridge
106
allows mapping of address space of one bus into the address space of the other bus through the use of internal configuration registers. Conventional PCI bridges are well known and is described, for example, in U.S. Pat. No. 5,918,026, entitled “PCI to PCI Bridge for Transparently Completing Transactions between Agents on Opposite Sides of the Bridge,” and in U.S. Pat. No. 5,905,877 entitled “PCI Host Bridge Multi-Priority Fairness Arbiter.” In addition, details of PCI specification and bus systems are described by Tom Shanley et al. in PCI System Architecture (3
rd
ed. 1995). The disclosures of these references are incorporated herein by reference.
One of the internal registers provided in the PCI-to-PCI bridge is the expansion ROM base address register
128
, which is coupled between the primary PCI interface
120
and an expansion ROM interface logic and device pins
130
. The expansion ROM base address register
128
typically stores the start memory address and size of the expansion ROM
132
. The expansion ROM interface logic and device pins provide interface to the expansion ROM
132
for accessing the stored device specific software. Additionally, the local CPU and chipset
116
also provided with the expansion ROM
134
, which stores device specific codes for the local CPU and chipset
116
. For example, device specific codes such as boot code, initialization code, BIOS, etc. may be stored in the expansion ROM
134
.
When the computer system
100
is powered on, the host CPU
102
copies the device specific code such as BIOS codes from the expansion ROM
132
. Concurrently, the local CPU and chipset
116
copies the device specific code from its expansion ROM
134
into its internal memory. The accessed device specific codes are then used to initialize the host computer and local CPU and chipset
116
.
However, one of the drawbacks of such computer system is cost. In particular, using separate expansion ROMs for the bridge
106
and local CPU and chipset
116
entails substantial cost. Additionally, the expansion ROMs
132
and
134
requires a dedicated interface circuits and logic to communicate with the bridge and local CPU and chipset
116
, respectively. Furthermore, manufacturers are increasingly phasing out small expansion ROMs as they move to larger expansion ROMs. Since the expansion ROMs, particularly for expansion ROM
132
for the PCI bridge, tends to be small in size, using a large dedicated expansion ROM for the PCI bridge results not only in higher cost but also leads to a waste of ROM space.
Thus, what is needed is a PCI subsystem that allows the host computer and the local CPU and chipset to initialize efficiently at boot-up without the cost associated with using multiple expansion ROMS.
SUMMARY OF THE INVENTION
The present invention fills these needs by providing an intelligent expansion ROM sharing bus subsystem. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.
In one aspect of the inventi

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