Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-09-20
2005-09-20
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06948142
ABSTRACT:
A method of protecting a net of an integrated circuit against injected crosstalk delay includes receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure. The signal path structure is analyzed to calculate a skew correction and a net ramptime for the selected net. An injected crosstalk delay of the selected net is estimated from a net aggressor. A crosstalk protection scheme is selected for the selected net to minimize chip area of the integrated circuit while ensuring that the injected crosstalk delay of the selected net does not exceed the value of maximum allowable injected crosstalk delay.
REFERENCES:
patent: 6721930 (2004-04-01), Sasaki et al.
M. Cuviello et al., Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects, Proceedings of the 1999 IEEE/ACM International Conference on Compute-Aided Design, pp. 297-303, Nov. 1999.
Molina, Jr. Ruben
Tetelbaum Alexander
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