Intelligent electrically erasable, programmable read-only memory

Details Intelligent electrically erasable, programmable read-only memory Intelligent electrically erasable, programmable read-only memory

1987-12-21

1991-07-23

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Including signal comparison

36518905, 365218, G11C 700

Patent

active

050349228

ABSTRACT:
An intelligent electrically erasable, programmable read-only memory achieves improved worst-case read operation latency by allowing for the interruption of write operations by subsequently received read requests. In the preferred embodiment, a state machine controller executes write operations by an iterative process of write pulses and write verify cycles. In addition, cells are erased prior to being written to by a similar iterative process. Both the write operations and the erase operations may be interrupted by read requests received after the write operation has begun execution. To avoid reading incorrect data in the case of a read operation at the same address as an interrupted write operation, a comparator matches read operation addresses with latched write operation addresses and provides the read operation data from a write data latch in the case of a match.

REFERENCES:
patent: 4249250 (1981-02-01), Scowen et al.
patent: 4410965 (1983-10-01), Moore
patent: 4460982 (1984-07-01), Gee et al.
patent: 4811294 (1989-03-01), Kobayashi et al.

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