Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
2000-11-03
2002-04-09
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S022000, C710S026000, C711S219000
Reexamination Certificate
active
06370601
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a direct memory access controller (DMAC) and more particularly to an intelligent DMAC.
BACKGROUND OF THE INVENTION
Direct Memory Access (DMA) is a method for direct movement of data between two components, for example in a computer system. Specifically, the data is moved between the components via a bus without program intervention. A DMA Controller (DMAC) is typically a memory-mapped peripheral device that performs memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral data transfers. The specialized hardware of the DMAC maximizes utilization of the system bus so that transfers are performed quickly and efficiently. In this manner, DMA operations typically outperform data movement operations performed by a CPU. Additionally, DMA operations free up the CPU to do other operations.
FIG. 1
illustrates a typical prior art DMAC
100
instantiated into a conventional computing system including a CPU
110
, a memory
120
, and a peripheral device
130
. CPU
110
executes the software instructions of the computing system, whereas memory
120
stores data and instructions for the computing system. Peripheral device
130
generally expresses output signals of or provides input signals to the computing system. Examples of peripheral device
130
include graphics cards, keyboard interfaces, and disk I/Os. The computing system further includes at least one bus
140
which facilitates communication between the various elements. For example, CPU
110
utilizes bus
140
to communicate data to or from peripheral device
130
. Most prior art DMACs rely on bus
140
to conduct the DMA operation.
DMAC
100
typically includes a set of registers which hold information necessary to the DMA operation. For example, DMAC
100
includes a source register (Src)
101
for storing the contents of the source address of the DMA bus cycles, a destination register (Dest)
102
for storing the contents of the destination address of the DMA bus cycles, and a length register (Len)
103
for storing the number of pieces of data to transfer. In this embodiment, DMAC
100
also includes a next register (Next)
104
for storing the address of the next place in memory where the DMACs parameters are stored (explained in detail below). Note that herein the term “registers” may include counters, registers, or a combination therein.
A single channel DMAC contains one set of registers
101
-
104
. Many prior art DMACs support multiple channels which are represented in
FIG. 1
as the dashed line boxes under DMAC
100
. In a typical multiple channel DMAC, registers
101
-
104
are simply instantiated once per channel. Thus, a four channel DMAC would include four sets of registers
101
-
104
.
FIG. 2A
is a typical example of the hierarchy of software and hardware in a conventional computing system. At the bottom of the hierarchy is hardware
200
, typically the actual hardware in the computing system. A register interface
250
facilitates communication between hardware
200
and the software of the system.
Continuing up the hierarchy, driver software
210
is considered the software that communicates with, i.e. reads and writes to, hardware
200
. Typically, driver software
210
is highly specialized software that is specific to the actual hardware of the computing system. For example, the driver software in an Apple Macintosh model 9500/120 computer cannot generally be used in place of the driver software in a Toshiba model Tecra 730 computer. However, hardware and software manufactures have gone to great lengths to standardize register interface
250
so that they can reuse driver software
210
in a variety of different computing systems. Examples of driver software
210
include hard disk drivers, floppy disk drivers, serial port drivers, parallel port drivers, graphics port drivers, and mouse drivers.
An Application Programming Interface (API)
240
is provided between driver software
210
and operating system software
220
as well as between operating software
220
and application software
230
. API
240
is a means of communicating between various layers of software. Specifically, API
240
refers to a standardized means of passing data between two different pieces of software. Operating system software (also referenced herein as OS software)
220
is the layer of software which generally handles the tasks of the computing system. These tasks would include items such as opening a file for input, prioritizing interrupts to the system, and scheduling events for later processing. Examples of current operating systems include: Apple Computer, Inc. MacOS Version 8.1; Sun, Inc. SunOS Version 5.5.1, and Microsoft, Inc. Windows '95.
OS software
220
communicates with driver software
210
and with application software
230
using different APIs
240
. Each API
240
is different because of different data communication needs. For example, OS software
220
generally communicates only data to driver software
210
, with a small overhead of control information. In contrast, OS software
220
often communicates task information to and/or from application software
230
, even though a high percentage of that task information is data.
Application software
230
is generally the highest level of software in a computing system. Typically, the user of the computing system communicates with application software
230
using a graphical user interface. Illustrative application software, such as Claris, Inc. ClarisWorks 4.0 (a word processing program), allows the user to open a text file, read the file, view the file, make changes to the file, save the file, and print the file. Based upon the specific requests of the user, application software
230
makes calls to OS software
220
via API
240
B to accomplish one or more of the above tasks. However, typically application software
230
is still responsible for the actual processing of the data. In some computing systems, OS software
220
is used to help draw graphics and text on the screen. In this manner, application software
230
is not burdened with extra software that could be standardized for other applications. Note that although
FIG. 2A
shows a single application software
230
, in general, a set of application software
230
actually communicates via a set of APIs
240
B to OS software
220
.
FIG. 2B
illustrates API
240
A between OS software
220
and driver software
210
in more detail. In API
240
A, four basic functions have been defined as a means of communication between the two software layers. These four functions are: Open, Close, Read, and Write. The Open function is used by OS software
220
to initialize driver software
210
for its first usage. Similarly, the Close function is used by OS software
220
to halt the operation of driver software
210
. These functions are typically used by OS software
220
to dynamically start and stop software drivers so that the computing system resources can be shared by various higher level software. In addition to the Open and Close functions, this API
240
A includes Read and Write functions which are generally used to either write data to or read data from hardware
200
via driver software
210
.
FIG. 2B
illustrates a number of parameter blocks (PBs), wherein PBs are generally designated locations in memory for specific parameters. For example, in a DMA transfer, the source address, destination address, and length of the transfer need to be designated. These values are placed in memory locations (i.e. PBs). These memory locations are predefined so that the memory can efficiently communicate the data to software (note that the software has had knowledge imparted to it that describes which locations of the PB contain which important data).
A DMAC process typically takes place in three stages: initialization, data transfer, and termination. Referring back to
FIG. 1
, during the initialization stage, CPU
110
sets up the DMA process by loading source register
101
with a starting source data address, de
Cao Chun
Harms, ESQ Jeanette S.
Lee Thomas
Xilinx , Inc.
LandOfFree
Intelligent direct memory access controller providing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Intelligent direct memory access controller providing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Intelligent direct memory access controller providing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2930640