Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2011-06-07
2011-06-07
Le, Don P (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S041000
Reexamination Certificate
active
07956639
ABSTRACT:
An apparatus and method controlling cellular automata containing a plurality of cascaded circuit cells having logic units. The cells are interleaved in groups toward supporting multiple directions, for example quad cells in which each cells of the quad is directed in a different directions separated by a fixed angle, such as 90 degrees (i.e., north, east, south, and west). These cells are triggered asynchronously as each cell is stabilized in preparation for receiving the trigger. The cells process data selectively based on the configuration of the cell and in response to receipt of data and trigger (or combined data and trigger) conditions from neighboring cells. The array can be utilized within a wide range of digital logic. As there is no need for distributing a global clock across the array of cells, the size of the array can be extended to any desired dimension.
REFERENCES:
patent: 5500609 (1996-03-01), Kean
patent: 5646545 (1997-07-01), Trimberger et al.
patent: 5761483 (1998-06-01), Trimberger
patent: 5861761 (1999-01-01), Kean
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6215327 (2001-04-01), Lycke
patent: 6288568 (2001-09-01), Bauer et al.
patent: 6308208 (2001-10-01), Jung et al.
patent: 6331788 (2001-12-01), Lycke
patent: 6388466 (2002-05-01), Wittig et al.
patent: 6732336 (2004-05-01), Nystrom et al.
patent: 6891395 (2005-05-01), Wells et al.
patent: 6949954 (2005-09-01), Nystrom et al.
patent: 7028107 (2006-04-01), Vorbach et al.
patent: 7058918 (2006-06-01), Abramovici et al.
patent: 7157934 (2007-01-01), Teifel et al.
patent: 7187201 (2007-03-01), Trimberger
patent: 7212448 (2007-05-01), Trimberger
patent: 7250786 (2007-07-01), Trimberger
patent: 7266020 (2007-09-01), Trimberger
patent: 7348796 (2008-03-01), Crouch et al.
patent: 7411436 (2008-08-01), Fang et al.
patent: 7429884 (2008-09-01), Ebergen et al.
patent: 2007/0094166 (2007-04-01), Addison
patent: 2007/0115040 (2007-05-01), Ebergen et al.
patent: 2007/0252617 (2007-11-01), Lewis et al.
patent: 2010/0102848 (2010-04-01), Gershenfeld et al.
patent: 2010/0308858 (2010-12-01), Noda et al.
Adachi, S. et al. “Computation by Asynchronously Updating Cellular Automata” Journal of Statistical Physics, vol. 114, No. 1-2, 99.0261-289, Jan. 2004.
Mahram, A. et al. “An Asynchronous FPGA Logic Cell Implementation” Proc of the 17th ACM Great Lakes Symposium on VLSI, pp. 176-179, 2007.
Traver, C. et al. “Cell Designs for Self-timed FPGAs” Proc of the 2001 ASIC/SOC Conference.
Fang, D. et al. “Self-Timed Thermally Aware Circuits” Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Karlsruhe, Mar. 2006.
Di, J. et al. “Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems” Journal Electronic Testing: Theory and Applications, pp. 175-192, 2007.
Nakada, H. et al. “Plastic Cell Architecture: A Dynamically Reconfigurable Hardware-based Computer” 6th Reconfigurable Architecture Workshop, in LNCS No. 1586, pp. 679-687, 1999.
Lycke, J. et al. “Reconfigurable Cellular Array Architecture for Molecular Electronics” Final Report, Air Force Research Laboratory, Mar. 2001.
Teifel, J. et al. “Automated Synthesis for Asynchronous FPGAs” 13th ACM International Symposium on Field-Programmable Gate Arrays, Feb. 2005.
Teifel, J. et al. “Programmable Asynchronous Pipeline Arrays” 13th International Conference on Field Programmable Logic and Applications Sep. 2003.
Macias, N. J. “The PIG Paradigm, The Design and Use of a Massively Parallel Fine Grained Self-Reconfigurable Infinitely Scalable Architecture” Proceedings of 1st NASA/DOD workshop, p. 175, 1999.
Durbeck, L.J.K. et al. “The Cell Matrix: Architecture for Nanocomputing” Nanotechnology 12, pp. 217-230, Aug. 2001.
Ebergen, J. et al. “Notes on Pulse Signaling” 13th IEEE Int'l Symposium on Asynchronous Circuits and Systems pp. 15-24, Mar. 2007.
Peper, F. et al. “Laying Out Circuits on Asynchronous Cellular Arrays: a Step Towards Feasible Nanocomputers?” Nanotechnology 14, pp. 469-485, Mar. 2003.
Hauck, S. “Asynchronous Design Methodologies: An Overview” Proc. of the IEEE, vol. 83, No. 1, pp. 69-93, Jan. 1995.
Hauck, S. et al. “An FPGA for Implementing Asynchronous Circuits” IEEE DEsign & Test of Computers, vol. 11, No. 3, pp. 60-69, Fall 1994.
Pavicic Mark J.
You Chao
Le Don P
NDSU - Research Foundation
O'Banion John P.
LandOfFree
Intelligent cellular electronic structures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Intelligent cellular electronic structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Intelligent cellular electronic structures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2641833