Integration scheme using self-planarized dielectric layer...

Details Integration scheme using self-planarized dielectric layer... Integration scheme using self-planarized dielectric layer...

2005-04-05

2005-04-05

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C427S255280

Reexamination Certificate

active

06875558

ABSTRACT:
A method for forming a trench isolation structure on a substrate. The method includes applying a pad oxide layer (226) on the substrate (224), applying a polysilicon layer (228) over the pad oxide layer, and applying a CVD anti-reflective coating (ARC) (230) over the polysilicon layer. A photoresist is formed on the CVD ARC and a trenched is etched at a desired location. One embodiment provides a method for depositing a trench oxide filling layer (300) on the trenched substrate utilizing the surface sensitivity of dielectric materials such as O3/TEOS to achieve a substantially self-planarized dielectric layer. Prior problems with porous trench fill, particular near trench corners, are obviated by use of the polysilicon layer. After deposition, an oxidizing anneal can be performed to grow a thermal oxide (307) at the trench surfaces and densify the dielectric material. A chemical mechanical polish can be used to remove the excess oxide material, including the porous regions.

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patent: 0 819 786 (1998-01-01), None
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