Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-08-13
2001-01-23
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S309000, C257S068000, C257S532000
Reexamination Certificate
active
06177696
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor integrated circuit devices and, more specifically, to deep trench (DT) capacitors formed within an integrated circuit. The present invention also relates to the method for producing such deep trench capacitors within a semiconductor integrated circuit.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuit memory devices store memory in the form of charge stored on a capacitor. The increases in integration density achieved in integrated circuits in recent years have been somewhat limited by the amount of charge which can be stored in capacitors within a given surface area. To meet the needs of increased integration, the amount of charge stored within a given surface area of a semiconductor integrated circuit device must be increased.
To increase the amount of charge stored by capacitors within a fixed surface area in a memory cell, the options are: (1) reduce the dielectric thickness, (2) increase the dielectric constant by changing to a different dielectric material, or (3) increase the surface area of the capacitor. The first option, reducing the thickness of the dielectric layer, results in increased leakage currents which can reduce the memory retention performance and adversely impact the reliability of the device. Changes to alternate dielectric materials require significant process development, new integration schemes, and new technology with a significant impact on the cost of production. Thus, the third option of increasing the surface area of the capacitor is the most desirable way to increase the amount of charge stored within a given surface area.
Trench capacitors have gained in popularity in recent years; they provide a structure that dramatically increases the amount of charge stored per semiconductor substrate surface area. As the depth of the trench increases, so, too, does the amount of charge stored within a fixed surface area. The technique of increasing the capacitor area for a trench capacitor by creating deeper trenches is limited, however, by manufacturing costs associated with the silicon etch processes involved in deep trench formation.
The technique is also limited by the processing technologies available for forming a capacitor within the deep trench once the trench is formed. As the aspect ratio of a trench capacitor increases (the depth of the trench increases relative to the width), it becomes increasingly difficult to form a capacitor within the trench. Formation of the capacitor within the trench generally requires manufacturing a plate within the trench, adding a dielectric within the trench, and then adding another plate within the trench. The inability to control the processes required to produce such structures within a trench is exacerbated as critical dimensions shrink. In addition, such processes further complicate the implementation of using deeper trenches to increase capacitance.
The prior art provides methods for forming a deep trench capacitor. An attractive method for increasing the amount of charge stored within a given size trench, and also the memory stored, involves the use of a capacitor plate or plates which contain textured surfaces. A textured surface increases the amount of exposed, effective charge-storing area within a given cross-sectional area. Thus, it is desirable to produce a capacitor in which the depth of the trench is maximized and the texture of the capacitor plate on which the dielectric is deposited, is also maximized. The ability to manufacture such a trench capacitor is limited by the processing technology available, as described above.
The ability to store charge is compromised when the charge stored is depleted because of the physical structure of the capacitor in which it is stored. As processing complexities in integration increase the need to incorporate a greater charge-storing capacity within a given surface area, it becomes increasingly more important to minimize the amount of charge depleted when being stored within a capacitor.
As device sizes and critical dimensions shrink and advances are made in device integration, associated advances in processing technology must also be made. In the semiconductor industry, the advances made in device integration are limited by the processing technology available to produce these devices. Therefore, it is an object of the present invention to provide associated manufacturing processes which are capable of producing the newly designed structure required by advanced integration. This object applies both to individual processes and to the process sequence used. The current art is limited by the processing technology available to create the devices required within the advanced integration scheme.
SUMMARY OF THE INVENTION
To achieve this and other objects, and in view of its purposes, the present invention provides an improvement to the existing deep trench capacitor technology existing in current art. The improvement consists of increasing the effective capacitor plate area for a given trench size, and incorporating a buried plate to minimize charge depletion. The present invention also provides a reliable and repeatable process sequence for producing these deep trench capacitors.
Specifically, the present invention involves the fabrication of a deep trench capacitor device wherein one of the capacitor plates is formed of hemispherical-grained silicon. The hemispherical-grained silicon is formed from an amorphous silicon film which is deposited onto the substrate and into the trench. One of the electrode plates of the capacitor is formed from a portion of the hemispherical-grained silicon film together with a “buried plate.” The buried plate is formed by doping the semiconductor material forming the wall around the trench. The portion of the hemispherical-grained silicon film in contact with the buried plate is doped with the same impurity type as is the buried plate. Together, the doped portion of the hemispherical-grained silicon and the buried plate combine to form one plate of the capacitor.
The present invention also includes a dielectric node material in the trench. The dielectric material covers at least a portion of the hemispherical-grained silicon and buried plate. A conductive material fills the trench to form a second plate of the capacitor so that the dielectric material is disposed between the first plate of the capacitor and the second plate of the capacitor.
REFERENCES:
patent: 5191509 (1993-03-01), Wen
patent: 5429972 (1995-07-01), Anjum et al.
patent: 5444013 (1995-08-01), Akrum et al.
patent: 5595926 (1997-01-01), Tseng
patent: 5665622 (1997-09-01), Muller et al.
Bronner Gary B.
Economikos Laertis
Jammy Rajarao
Park Byeongju
Radens Carl J.
Capella, Esq. Steven
International Business Machines - Corporation
Ratner & Prestia
Wojciechowicz Edward
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