Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-01-31
2006-01-31
Goudreau, George A. (Department: 1763)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S692000, C438S694000, C438S700000, C438S780000, C438S789000
Reexamination Certificate
active
06992003
ABSTRACT:
A backend semiconductor fabrication process includes forming an interlevel dielectric (ILD) overlying a wafer substrate by forming a low K dielectric (K<3.0) overlying the substrate of the wafer, forming an organic silicon-oxide glue layer overlying the low K dielectric, and forming a CMP stop layer dielectric overlying the glue layer dielectric. A void is then formed in the ILD, a conductive material is deposited to fill the void, and a polish process removes the excess conductive material. Forming the glue layer dielectric and the CMP stop layer dielectric is achieved by forming a CVD plasma using an organic precursor and an oxygen precursor and maintaining the plasma through the formation of the glue layer dielectric and the stop layer. The flow rate of the organic precursor is reduced relative to the oxygen precursor flow rate to form a CMP stop layer that is substantially free of carbon.
REFERENCES:
patent: 6153512 (2000-11-01), Chang et al.
patent: 6197704 (2001-03-01), Endo et al.
patent: 6303525 (2001-10-01), Annapragada
patent: 6331480 (2001-12-01), Tsai et al.
patent: 6348407 (2002-02-01), Gupta et al.
patent: 6383913 (2002-05-01), Tsai et al.
patent: 6383950 (2002-05-01), Pangrle et al.
patent: 6440878 (2002-08-01), Yang et al.
patent: 6455443 (2002-09-01), Eckert et al.
patent: 6465372 (2002-10-01), Xia et al.
patent: 6472335 (2002-10-01), Tsai et al.
patent: 6486061 (2002-11-01), Xia et al.
patent: 6602779 (2003-08-01), Li et al.
patent: 6764774 (2004-07-01), Grill et al.
patent: 2005/0023689 (2005-02-01), Nicholson et al.
Junker Kurt H.
Spencer Gregory S.
Vires Jason A.
Freescale Semiconductor Inc.
Goudreau George A.
Lally Joseph P.
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