Integration of spin-on gap filling dielectric with W-plug withou

Details Integration of spin-on gap filling dielectric with W-plug withou Integration of spin-on gap filling dielectric with W-plug withou

1996-06-10

1998-12-15

Green, Anthony J.

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438631, 438633, 438634, 438639, 438692, 438697, 438700, 438702, H01L 21306

Patent

active

058496378

ABSTRACT:
A via hole for a metal contact is formed by depositing a metal layer on the surface of a semiconductor device structure; depositing a thick PECVD oxide on the metal layer; patterning the metal layer using photolithography and etching so that what remains after this step is patterned metal regions such as lines or pads, each of which metal regions is covered by a thick PECVD oxide; creating islands of PECVD oxide using a photolithography process on the patterned metal regions at locations where it is desired to form via holes, the remainder of the patterned metal regions being covered with a thin PECVD oxide under layer; depositing a spin-on planarization material, such as SOG or low K polymer resulting in only a thin layer of spin-on material on top of the islands; using a partial etchback, removing the SOG from the top of the islands; depositing a PECVD oxide capping layer and polishing the capping layer using CMP; and then forming the via holes in the PECVD islands. The result is a via hole whose side walls are covered with a high quality PECVD oxide. Thereafter, the via hole can be filled with a W-plug without a problem of outgassing from a spin-on material such as SOG or low K polymer.

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