Integration of SiGe NPN and vertical PNP devices on a substrate

Details Integration of SiGe NPN and vertical PNP devices on a substrate Integration of SiGe NPN and vertical PNP devices on a substrate

2005-03-17

2009-06-02

Luu, Chuong A. (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C257S197000, C257S565000, C257S552000

Reexamination Certificate

active

07541231

ABSTRACT:
According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.

REFERENCES:
patent: 6933202 (2005-08-01), Hurwitz et al.
patent: 2003/0219952 (2003-11-01), Fujimaki et al
patent: 2004/0099895 (2004-05-01), Gray et al.
Baudry, et al.BiCMOS7RF:A Highly-Manufacturable 0.25-/spl mu/m BiCOMOS RF-Applications-Dedicated Technology Using Non Selective SiGe: C Epitaxy, Proceedings of the 2003 Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, France, IEEE BCTM 11.3; pp. 207-210 (Sep. 2003).
Baudry, et al.High Performance 0.25/spl mu/m SiGe and SiGe: C HBTs Using Non Selective Epitaxy, Proceedings of the 2001 Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, MN, IEEE BCTM 3.1; pp. 52-55 (Sep. 2001.

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