Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-15
2001-02-13
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S361000, C257S362000, C257S497000, C257S498000, C257S499000, C257S336000, C257S337000, C257S338000, C257S444000, C257S408000, C257S368000, C257S900000, C257S374000, C257S396000, C257S397000, C257S398000
Reexamination Certificate
active
06188110
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to integrated circuit manufacture; and more particularly to a method of manufacture and a structure in which isolation regions and epitaxial growth regions are integrated to produce active devices having enhanced performance.
2. Description of the Related Art
The structure and the various components, or features, of a metal oxide semiconductor (MOS) devices are generally well known. A MOS transistor typically includes a substrate material onto which a gate insulator and a patterned gate conductor are formed. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source/drain regions. The gate conductor is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS transistor employs n-type junctions placed into a p-type substrate. Conversely, a typical p-channel MOS transistor comprises p-type junctions placed into an n-type substrate. The substrate comprises an entire monolithic silicon wafer, of which, a portion of the substrate known as a “well” exists. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junction in the non-well areas. Accordingly, wells are often employed when both n-type and p-type transistors (i.e., Complementary MOS, “CMOS”) are needed.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductors, source/drain junctions, and interconnects to the junctions must be made as small as possible. Many modern day processes employ features which have less than 0.15 microns critical dimensions. As feature size decreases, the size of the resulting transistors as well as the interconnects between transistors also decrease. Smaller transistor size allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single and relatively small die area. Further, smaller transistors typically have lower turn-on threshold voltages, faster switching speeds and consume less power in their operation. These features in combination allow for higher speed integrated circuits to be constructed that have greater processing capabilities and that produce lesser heat.
The benefits of high density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the higher resolutions needed for submicron features. To some extent, wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, silicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
Many other techniques are often used to achieve a higher density circuit. However, these techniques must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot, in all instances, offset the problems associated with small features or features arranged extremely close to one another. For example, as the channel length decreases, short channel effects (“SCE”) generally occur. SCE cause threshold voltage skews at the channel edges as well as excessive subthreshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection (“HCI”). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric fields give rise to so called hot carriers and the injection of these carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since these carriers can become trapped and skew the turn-on threshold voltage of the ensuing transistor.
As feature sizes decrease, other components formed on the substrate must be formed to have a minimal effect on the smaller active devices. For example, isolation regions formed during oxide growth steps according to the well-known LOCOS process can extend into active regions of transistors, such extensions commonly referred to as a “bird's beak.” The bird's beak extends into the active regions by a distance that is in proportion to the field dielectric thickness. This non-uniform junction between the active regions and the isolation regions causes the active regions to be non-uniform, thus affecting their operational characteristics.
Another problem that often occurs during the formation of isolation regions is that added impurities in the substrate tend to migrate into the oxide region as it is formed thereby creating undesired electron/hole flow characteristics. For example, boron is known to rapidly migrate not only along the substrate surface, but also perpendicular to the surface as well. In the latter instance, perpendicular migration of impurities into the growing field oxide causes a phenomenon known as oxidation enhanced diffusion (OED). To minimize OED, light ion channel-stop species such as boron must be implanted sufficiently deep so that they are not absorbed by the growing field oxide. However, deep or heavy doping causes high source/drain-to-substrate pn junction breakdown voltages.
Yet another problem that occurs during the formation of isolation regions is the creation of Kooi ribbons. Kooi ribbons are areas within the semiconductor that are formed of NH
3
and silicon (Si), the NH
3
created. The NH
3
, after being created from a reaction of H
2
O and the masking silicon nitride Si
3
N
4
during the oxidation step, diffuses through the oxide and reacts with the silicon substrate to form the silicon nitride (Si
3
N
4
) Kooi ribbons. These Kooi ribbons typically form in the proximity of the active regions during the field oxidation process.
Generally, the problems that occur in growing field oxides occur as a result of undesirable growth of the oxide in unwanted directions or locations and by introduced impurities. For example, OED is a result of out-diffusion from channel-stop implant to overlying, growing field oxide. Kooi ribbons are a result of NH
3
diffusion from nitride-covered active regions through the pad oxide and into the active region during field oxide growth. Any gate oxide formed in the active area upon the ribbon locations are thinner and of lower quality than in other areas, causing low voltage breakdown of the gate oxide. Typically, a sacrificial gate oxide must be formed and thereafter stripped to remove the Kooi ribbon. Thus, this problem creates the need for additional processing steps and resources.
Thus, there exists a need in the art for better methods of forming isolation region/active regions.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the transistor formation process according to the present invention in which isolation regions and active regions are formed that each possess uniform and consistent geometric and material properties. The isolation process hereof is carried out without having to locally form dielectrics in the field regions, i.e., without locally growing oxides using the LOCOS process. Instead of locally oxidizing silicon in the field regions, the present process blanket forms a dielectric blanket layer across the entire wafer surface. The blanket-formed dielectric layer may include both a first dielectric layer and a second dielectric layer. The first dielectric layer is relatively thin and is much thinner than conventional field oxides. A second dielectric layer is then formed across the entire first dielectric layer and is thicker, as compared to the first dielectric layer.
The blanket-formed
Fulford Jr. H. Jim
Gardner Mark I.
Abraham Fetsum
Advanced Micro Devices
Barlick Bruce
Harrison James
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