Integration of high voltage lateral MOS devices in low voltage C

Details Integration of high voltage lateral MOS devices in low voltage C Integration of high voltage lateral MOS devices in low voltage C

1996-03-08

1997-07-22

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257408, 257399, 257394, 257344, 257345, 257488, H01L 2994

Patent

active

056506589

ABSTRACT:
Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage devices are to be formed. Such selective modification of an already existing mask set designed for low voltage CMOS typography allows additional doping of the substrate or provision of further overlay material to accommodate the effects of high voltage operation of selected areas of the water and thereby effectively performs precursor tailoring or modification of those portions of the wafer where a high voltage condition will be encountered.

REFERENCES:
patent: 5210437 (1993-05-01), Sawada et al.

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