Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-04-28
2001-08-28
Picard, Leo P. (Department: 2835)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S707000, C361S709000, C361S710000, C361S713000, C361S714000, C361S717000, C361S718000, C361S719000, C257S706000, C257S717000, C257S719000, C174S016300, C165S080200, C165S185000
Reexamination Certificate
active
06282096
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to schemes for integrating heat conducting promotion apparatus and substrates of an IC (integrated circuits) package, particularly to schemes of integrating a heat sink and a substrate in packaging flip chips for resolving problems arising from thermal stress.
BACKGROUND OF THE INVENTION
A conventional scheme of packaging a flip chip is shown in
FIG. 1
, where bumps
11
of flip chip
1
connect a surface
21
of substrate
2
, a heat sink
3
includes a first portion
31
located above the heat dissipation surface
12
of flip chip
1
, and a second portion
32
connected to the surface
21
through thermal paste
5
, with heat sink
3
usually connected to surface
12
by adhesive material
4
. The heat sink
3
in such a conventional package usually suffers warpage as shown in
FIG. 2
when there arises thermal stress with the chip
1
in the package, and may even break away from flip chip
1
or substrate
2
, resulting in very low adaptability of the package to environmental variation, and inevitably leading to extreme difficulty in predicting application reliability of the package product. Typical examples of this conventional scheme can be known from two prior arts: U.S. Pat. Nos. 5,724,729 and 5,587,882.
Although the prior art U.S. Pat. No. 5,311,402 differs from the aforementioned two prior arts, its scheme of integrating the so called “cap” and the substrate thereof is substantially similar to the aforementioned two prior arts, only with a difference that the cap thereof has its peripheral portion extending into the groove of the substrate thereof and being connected to the inner face of the groove through solder material. Such a package, when the chip therein suffers thermal stress, usually also has the cap thereof suffering warpage, resulting in low adaptability of the package to environmental variation, and inevitably leading to extreme difficulty in predicting application reliability of the package product.
To improve conventional schemes of packaging ICs including heat conducting promotion apparatus, the present invention suggests novel schemes of integrating heat conducting promotion apparatus (or those similar to the so called “cap” in U.S. Pat. No. 5,311,402) and substrates in packaging chips, enabling each manufacturer to select from among them the one most fitting individual conditions.
SUMMARY OF THE INVENTION
An object of the present invention is to provide chip packages in which heat conducting promotion apparatus and substrates are so integrated as to immunize the chip packages against application unreliability resulting from thermal stress.
Another object of the present invention is to provide several novel schemes of integrating heat conducting promotion apparatus and substrates in packaging chips, in order to enable each manufacturer to select from among these schemes the one most fitting its conditions, thereby the related industries may significantly promote the adaptability of chip packages to environmental variation, and the application reliability of chip packages can thus be greatly upgraded in simple, flexible, and economical ways.
A key difference between the present invention and conventional arts is that the heat conducting promotion apparatus and substrate in the chip packages suggested by conventional arts are connected through adhesive material or solder, while the chip package suggested by the present invention is characterized by its heat conducting promotion apparatus partly contacting a surface of its substrate and partly extending into a cavity of the substrate. The chip package suggested by the present invention is also characterized by the structure of its heat conducting promotion apparatus' part extending into the cavity and the different schemes of integrating its heat conducting promotion apparatus and substrate. For example, its heat conducting promotion apparatus' part extending into the cavity may be in a twisty shape, and may be connected to the inner face of the cavity through elastic paste, or be coupled with an elastic solid preset in the cavity. As a result of these features, the thermal stress suffered by the chips packaged according to the present invention can be absorbed by the twisty part of the heat conducting promotion apparatus, or by the elastic paste or the elastic solid, enabling related industries to promote the adaptability of chip packages to environmental variation in simple, economical, and flexible ways, leading to significant improvements in application reliability of chip packages.
The present invention may be typically represented by an electronic device such as a chip package product. The electronic device comprises:
at least a semiconductor unit (such as a chip) including a heat conducting surface (or heat dissipation surface) and a connecting portion (such as bump or bumps of a flip chip);
an object (such as a chip carrier, or specifically a substrate) including a connecting surface having at least one cavity, the connecting surface being attached by the connecting portion of the semiconductor unit; and
a heat conducting promotion apparatus (or heat sink) including a first part, a second part, and a third part, with the first part close to the heat conducting surface, the second part extending from the first part to the connecting surface, and the third part extending from the second part to the cavity.
REFERENCES:
patent: 4561001 (1985-12-01), Kohara et al.
patent: 5311402 (1994-05-01), Kobayashi et al.
patent: 5396403 (1995-03-01), Patel
patent: 5528462 (1996-06-01), Pendse
patent: 5587882 (1996-12-01), Patel
patent: 5875096 (1999-02-01), Gates
patent: 5889323 (1999-03-01), Tachibana
patent: 5926371 (1999-07-01), Dolbear
patent: 5931222 (1999-08-01), Toy et al.
patent: 6008536 (1999-12-01), Mertol
Lo Randy H. Y.
Wu Chi Chuan
Chervinsky Boris L.
Klarquist Sparkman Campbell & Leigh & Whinston, LLP
Picard Leo P.
Siliconware Precision Industries Co., LTD.
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