Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-12-30
2004-05-04
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S681000, C438S685000, C438S686000, C438S687000, C427S008000, C427S099300, C427S248100
Reexamination Certificate
active
06730598
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacturing and, in particular, to the integration of annealing capability into metal deposition tools or chemical mechanical polishing tools.
BACKGROUND OF THE INVENTION
In integrated circuit manufacturing processes, it is generally desirable to minimize the total number of steps in the process and the time between each step. While it is generally desirable to allow the greatest latitude in fabrication process parameters, in certain cases, known variations can be eliminated or controlled to an extent that provides a greater predictability of results of the process. One such variation occurs during the stabilization of metal films that are deposited on a wafer dielectric layer to form interconnects between active devices.
Integrated circuits (ICs) manufactured today generally include an elaborate system of metalized interconnects to couple the various devices that have been fabricated in the semiconductor substrate. The technology for forming these metalized interconnects is extremely sophisticated. Commonly, aluminum, copper or some other metal is deposited on a dielectric layer and then patterned to form interconnect paths. Another dielectric or insulation layer such as silicon dioxide (SiO
2
) is then deposited over this first metal layer (metal
1
); via openings are etched through the dielectric layer; and the second metal layer (metal
2
) is deposited. The metal
2
layer covers the dielectric layer and fills the via openings, making electrical contact down to the metal
1
layer. After a metal layer is deposited, the layer is usually planarized in a chemical mechanical polishing (CMP) process to remove the portions of the metal layer that do not form the desired interconnects such as lines or vias.
A considerable amount of effort in the manufacturing of modern complex, high density, multilevel interconnections is devoted to the planarization of the individual layers of the interconnection structure. Nonplanar surfaces create poor optical resolution of subsequent photolithographic processing steps. Poor optical resolution prohibits the printing of high density lines. Another problem with nonplanar surface topography is the step coverage of subsequent metalization layers. If a step height is too large there is a serious danger that open circuits will be created. Planar interconnect surface layers are a must in the fabrication of modern high density multilevel integrated circuits.
CMP employs polishing to remove protruding steps formed along the upper surface of the inter-layer dielectric. CMP is also used to “etch back” deposited metal layers to form planar plugs or vias. In a typical CMP process, a silicon substrate or wafer is placed face down on a rotating table or platform covered with a flat polishing pad that has been coated with an active slurry. A carrier, which is typically made of a thick, nonflexible metal plate, is used to apply a downward force against the backside of the substrate. The downward force and the rotational movement of the pad together with the slurry facilitate the abrasive polishing and planar removing of the upper surface of the thin metal film.
Nonuniform polishing can result in too much film being removed from some parts of the wafer and not enough film being removed from other parts. Also, lack of uniformity in the polishing rate from wafer to wafer can result in decreased process yield and reliability. Significant effort has been expended in attempts to control the polishing part of the process of integrated circuit manufacturing.
Electroplating is becoming the favored technique at least for copper deposition in the semiconductor industry. Electroplated copper, however, is known to be unstable at room temperature. Its physical properties such as resistivity and hardness continue to change with time. This process can last for weeks and can have significant impact on the stability of the subsequent process steps such as CMP. Annealing can accelerate the stabilization of the copper film, but adds an additional step in the process flow. Also, when annealing is performed by a separate annealing tool, the time between the deposition of the copper or metal layer can vary due to any number of reasons, such as unavailability of the annealing tools, imprecise scheduling or a physical distance between the annealing tool and the CMP tool.
Changes in the resistivity and hardness of the metal that has been deposited can affect the rate of polishing during the CMP portion of the process. It is desirable to minimize the variability of the stabilization of the metal. Annealing helps to stop the degradation or change in the properties of the metal. If the deposited metal is stabilized consistently, greater predictability can be achieved in the CMP process.
SUMMARY OF THE INVENTION
In one embodiment, an apparatus includes a metal deposition tool having annealing capability.
REFERENCES:
patent: 5882498 (1999-03-01), Dubin et al.
patent: 5943600 (1999-08-01), Ngan et al.
patent: 5968587 (1999-10-01), Frankel
patent: 5989999 (1999-11-01), Levine et al.
patent: 6017820 (2000-01-01), Ting et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Pham Long
Rao Shrinivas H
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