Integrating high performance and low power multi-gate devices

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S348000, C257S401000, C257S368000

Reexamination Certificate

active

07638843

ABSTRACT:
A semiconductor device comprises a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprises a first gate structure and the second multi-gate device comprises a second gate structure. An effective width of the first gate structure is greater than an effective width of the second gate structure.

REFERENCES:
patent: 2001/0002056 (2001-05-01), Manning
patent: 2008/0169511 (2008-07-01), Muller et al.
Hisamoto, et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20nm”, IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, p. 2320-2325.
Park, et al., Multiple-Gate SOI MOSFETs: Device Design Guidelines, IEEE Transactions on Electron Devices, vol. 49, No. 12, Dec. 2002, p. 2222-2229.
Yu, et al., “FinFET Scaling to 10nm Gate Length”, IEEE, 2002, pp. 251-254.
Chau, et al., “Advanced Depleted-Substrate Transistors: Single-Gate, Double-Gate and Tri-Gate”, 2002 International Conference on Solid State Devices and Materials (SSDM 2002), Nagoya, Japan, pp. 1-23.
Yang, et al., “25 nm CMOS Omega FETs,” IEEE, 2002, pp. 255-258.
Park, et al., “Pi-Gate SOI MOSFET”, IEEE, 2001, pp. 405-406.
Choi, et al., “FinFET Process Refinements for Improved Mobility and Gate Work Function Engineering,” IEEE, 2002, pp. 259-262.

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