Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2007-05-01
2007-05-01
Potter, Roy Karl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S778000
Reexamination Certificate
active
10980536
ABSTRACT:
Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described. Another exemplary embodiment illustrated the use of chip-scale processes for interconnecting discrete integrated circuits.
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patent: 6900538 (2005-05-01), Alter et al.
Dr. Luu Nguyen et al, Assembly Considerations for micro SMD Wafer-Level CSPs. Chip Scale Review, May/Jun. 2000, p. 48 et seq.
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Dr. Philip Garrou, Wafer-Level Packaging Has Arrived Semiconductor International, Oct. 2000, p. 119 et seq.
Alter Martin
Rumsey Robert
Ladas & Parry LLP
Micrel Incorporated
Potter Roy Karl
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