Integrated write/read memory

Details Integrated write/read memory Integrated write/read memory

1985-07-25

1988-04-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

371 10, G11C 700

Patent

active

047379359

ABSTRACT:
An integrated write/read memory consisting of a matrix of normal memory cells organized in rows and columns. The memory further includes a smaller matrix of redundant memory cells having their own column and row address decoders that can be engaged to replace any faulty memory cells in the normal matrix. The redundant address decoders are connected to all the address lines by means of fusible links so that any redundant address gate can be programmed to emulate the address of a faulty memory cell. The system further includes logic controls that automatically disables any normal memory address if a redundant memory cell is programmed to take its place.

REFERENCES:
patent: 4358833 (1982-11-01), Folmsbee et al.
patent: 4441170 (1984-04-01), Folmsbee et al.
Kim Kokkonen et al., "Redundency Techniques for Fast Static RAMs", 1981 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 18, 1981, pp. 80-81.
S. Sheffield Eaton et al., "A 100ns 64K Dynamic RAM Using Redundancy Techniques", 1981 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Fed. 18, 1981, pp. 84-85.

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