Integrated verification and manufacturability tool

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000

Reexamination Certificate

active

07017141

ABSTRACT:
An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

REFERENCES:
patent: 5031111 (1991-07-01), Chao et al.
patent: 6009251 (1999-12-01), Ho et al.
A. B. Kahng et al., “Subwavelength Lithography and its Potential Impact on Design and EDA,” 1999 ACM Design Automation Conference, pp. 799-804.
T. Mitsuhashi et al., “An Integrated MAsk Artwork Analysis System,” 1980 Proceedings of the 17th Design Automation Conference, pp. 277-284.
D. M. H. Walker et al., “A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator,” 1991 28th ACM/IEEE Design Automation Conference, Paper 34.2, pp. 579-584.
A. J. Strojwas et al., “VLSI: linking design and manufacturing,” IEEE Spctrum, Oct. 1988, pp. 24-28.
D. S. Harrison et al., “Electronic CAD Frameworks,” Proceeding of the IEEE, vol. 78., No. 2, Feb. 1990, pp. 393-417.
D. S. Boning et al., “The Intertool Profile Interchange Format: An Object-Oriented Approach,” IEEE Trans. on Computer-Aided Design vol. 10, No. 9, Sep. 1991, pp. 1150-1156.
D. M. H. Walker et al., “The CDB/HCDB Semiconductor Wafer Representation Server,” IEEE Trans. on Computer-Aided Desing of Integrated Circuits and Systems, vol. 12, No. 2, Feb. 1993, pp. 283-295.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Integrated verification and manufacturability tool does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated verification and manufacturability tool, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated verification and manufacturability tool will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3541900

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.